<*..\HARDWARE\TIMER\hal_timer.h ..\SYSTEM\sys\sys.h ..\USER\stm32f1xx.hd"..\USER\stm32f103xe.h..\CORE\core_cm3.hF:D:\application\keil5_34\ARM\ARMCC\Bin\..\include\stdint.h%..\CORE\cmsis_compiler.h"..\CORE\cmsis_armcc.h2'..\USER\system_stm32f1xx.hR?3..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h)..\USER\stm32f1xx_hal_conf.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h ..\USER\stm32f1xx.hdF:D:\application\keil5_34\ARM\ARMCC\Bin\..\include\stddef.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.hD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h|G;..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h:D8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.hqC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_eth.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_can.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cec.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_adc_ex.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_crc.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dac.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dac_ex.hE9..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.hH<..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.hD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_sram.hxC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_fsmc.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_nor.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h/C7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2s.hD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_iwdg.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rtc.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rtc_ex.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pccard.hB6..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_sd.hXD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_sdmmc.htD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_nand.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_spi.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.hF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.hD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.hoE9..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_usart.hD8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_irda.hI=..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_smartcard.h`D8..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_wwdg.hrC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pcd.hB6..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usb.hBF:..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pcd_ex.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_hcd.hC7..\HALLIB\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_mmc.h, ..\Middle\sys_timer\sys_timer.hb*..\HARDWARE\TIMER\hal_timer.cP__HAL_TIMER_H__P__SYS_HYP__STM32F1XX_HP __cplusplus PSTM32F1P STM32F103xEPUSE_HAL_DRIVERa%P__STM32F1_CMSIS_VERSION_MAIN%P__STM32F1_CMSIS_VERSION_SUB1(%P__STM32F1_CMSIS_VERSION_SUB2'#P__STM32F1_CMSIS_VERSION_RC P__STM32F1_CMSIS_VERSIONP__STM32F103xE_HXP __CM3_REVP__MPU_PRESENTP__NVIC_PRIO_BITSP__Vendor_SysTickConfigNonMaskableInt_IRQnHardFault_IRQnMemoryManagement_IRQnBusFault_IRQnUsageFault_IRQn5 SVCall_IRQn DebugMonitor_IRQnS PendSV_IRQn SysTick_IRQnb WWDG_IRQn PVD_IRQnJ TAMPER_IRQne RTC_IRQnK FLASH_IRQn RCC_IRQn\ EXTI0_IRQn EXTI1_IRQn EXTI2_IRQn EXTI3_IRQn EXTI4_IRQnDMA1_Channel1_IRQnDMA1_Channel2_IRQnDMA1_Channel3_IRQnDMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQn ADC1_2_IRQnUSB_HP_CAN1_TX_IRQnUSB_LP_CAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQn EXTI9_5_IRQn%TIM1_BRK_IRQn TIM1_UP_IRQn TIM1_TRG_COM_IRQn} TIM1_CC_IRQn, TIM2_IRQn TIM3_IRQn TIM4_IRQn I2C1_EV_IRQnC I2C1_ER_IRQnG I2C2_EV_IRQnB I2C2_ER_IRQnF SPI1_IRQn SPI2_IRQn USART1_IRQnn USART2_IRQnm USART3_IRQnlEXTI15_10_IRQnRTC_Alarm_IRQnUSBWakeUp_IRQnTIM8_BRK_IRQn TIM8_UP_IRQnTIM8_TRG_COM_IRQnv TIM8_CC_IRQn% ADC3_IRQn7 FSMC_IRQn  SDIO_IRQn TIM5_IRQn SPI3_IRQn UART4_IRQn UART5_IRQn TIM6_IRQn TIM7_IRQnDMA2_Channel1_IRQnDMA2_Channel2_IRQnDMA2_Channel3_IRQnDMA2_Channel4_5_IRQn8 IRQn_TypeP__CORE_CM3_H_GENERICP __stdint_hP__ARMCLIB_VERSIONlP__INT64_TYPE__;P__INT64P__INT64_C_SUFFIX__P __PASTE2NP__PASTEP __INT64_CP __UINT64_CP__ARMCC_VERSIONP __LONGLONGP__STDINT_DECLSQP __CLIBNSBint8_tint16_tnint32_tpint64_tkuint8_t( uint16_t uint32_t uint64_t int_least8_tint_least16_tint_least32_tint_least64_tuint_least8_tuint_least16_tsuint_least32_tuuint_least64_tp int_fast8_t int_fast16_tW int_fast32_tY int_fast64_tT uint_fast8_tuint_fast16_tuint_fast32_tuint_fast64_tP __sizeof_ptr intptr_t} uintptr_t intmax_t uintmax_tP INT8_MINUP INT16_MIN$P INT32_MIN&P INT64_MIN!P INT8_MAXSP INT16_MAX"P INT32_MAX$P INT64_MAXP UINT8_MAXP UINT16_MAXP UINT32_MAXP UINT64_MAXPINT_LEAST8_MINqPINT_LEAST16_MIN@PINT_LEAST32_MINBPINT_LEAST64_MIN=PINT_LEAST8_MAXoPINT_LEAST16_MAX>PINT_LEAST32_MAX@PINT_LEAST64_MAX;PUINT_LEAST8_MAXPUINT_LEAST16_MAXPUINT_LEAST32_MAXPUINT_LEAST64_MAXPINT_FAST8_MINPINT_FAST16_MINPINT_FAST32_MINPINT_FAST64_MINPINT_FAST8_MAXPINT_FAST16_MAXPINT_FAST32_MAXPINT_FAST64_MAXPUINT_FAST8_MAXePUINT_FAST16_MAX4PUINT_FAST32_MAX6PUINT_FAST64_MAX1P INTPTR_MINP INTPTR_MAXP UINTPTR_MAX:P INTMAX_MINP INTMAX_MAXP UINTMAX_MAXJP PTRDIFF_MINcP PTRDIFF_MAXaPSIG_ATOMIC_MINmPSIG_ATOMIC_MAXkP SIZE_MAX;P WCHAR_MINP WCHAR_MAXP WINT_MIN6P WINT_MAX4PINT8_CPINT16_CPINT32_CPINT64_CPUINT8_CP UINT16_CrP UINT32_CtP UINT64_CoP INTMAX_CHP UINTMAX_C!P__CM3_CMSIS_VERSION_MAIN3 P__CM3_CMSIS_VERSION_SUBpP__CM3_CMSIS_VERSIONP __CORTEX_MxP __FPU_USED~P __CC_ARM6P__CMSIS_COMPILER_H P__CMSIS_ARMCC_HP__TARGET_ARCH_7_McP__ARM_ARCH_7M__P__ASM"P __INLINE>P__STATIC_INLINE P__STATIC_FORCEINLINEP __NO_RETURNP__USEDP__WEAKP __PACKEDUP__PACKED_STRUCTP__PACKED_UNIONaP__UNALIGNED_UINT32N!P__UNALIGNED_UINT16_WRITEV P__UNALIGNED_UINT16_READ!P__UNALIGNED_UINT32_WRITEX P__UNALIGNED_UINT32_READP __ALIGNEDP __RESTRICT__get_CONTROL\ " __regControl __set_CONTROLP, "control " __regControl  __get_IPSRE " __regIPSR __get_APSRM " __regAPSR __get_xPSR " __regXPSR __get_PSP# "__regProcessStackPointer __set_PSP, "topOfProcStack&# "__regProcessStackPointer __get_MSP "__regMainStackPointero __set_MSP, "topOfMainStack0 "__regMainStackPointerm__get_PRIMASKf " __regPriMask!__set_PRIMASKZ, "priMask " __regPriMaskP__enable_fault_irq\P__disable_fault_irq__get_BASEPRIw " __regBasePri+__set_BASEPRIk, "basePri " __regBasePri)__set_BASEPRI_MAX, "basePri "__regBasePriMax__get_FAULTMASK "__regFaultMask=__set_FAULTMASK, " faultMask "__regFaultMask __get_FPSCR __set_FPSCR, "fpscrP__NOPP__WFIP__WFE!P__SEVP__ISB%P__DSB*P__DMB0P__REVP__NO_EMBEDDED_ASM__REV16, "value__REVSH, "valueP__RORP__BKPTP__RBITP__CLZP __LDREXB<P __LDREXH6P __LDREXW'P __STREXB%P __STREXHP __STREXWP__CLREXP__SSATP__USAT__RRX0, "valueP__LDRBTP__LDRHTP__LDRTP__STRBTpP__STRHTjP__STRTP__CMSIS_GENERICP__CORE_CM3_H_DEPENDANT P__I P__O P__IOm P__IMo P__OMiP__IOM8 S8 Q " _reserved0 "Q "V "C "Z "N "b "w APSR_TypeP APSR_N_PosCP APSR_N_MskJP APSR_Z_Pos7P APSR_Z_Msk>P APSR_C_PosNP APSR_C_MskUP APSR_V_Pos;P APSR_V_MskBP APSR_Q_Pos@P APSR_Q_MskG8 S8 Q "ISR  " _reserved0 "b "w IPSR_TypeP IPSR_ISR_PosP IPSR_ISR_Msk8 S8 Q "ISR " _reserved0 " ICI_IT_1 " _reserved1 "T " ICI_IT_2 "Q "V "C "Z "N "b "w xPSR_TypeP xPSR_N_Pos P xPSR_N_MskP xPSR_Z_PosP xPSR_Z_MskP xPSR_C_PosP xPSR_C_MskP xPSR_V_PosP xPSR_V_Msk P xPSR_Q_Pos P xPSR_Q_MskPxPSR_ICI_IT_2_PosPxPSR_ICI_IT_2_MskP xPSR_T_PosP xPSR_T_Msk PxPSR_ICI_IT_1_PosPxPSR_ICI_IT_1_MskP xPSR_ISR_PoshP xPSR_ISR_Msko8 S8 Q "nPRIV "SPSELD " _reserved1 "b` "w] CONTROL_TypePCONTROL_SPSEL_PosPCONTROL_SPSEL_MskPCONTROL_nPRIV_PosPCONTROL_nPRIV_Msk8 Q <" ISERA <"` RESERVED0 <" ICERQ <"` RSERVED1 <" ISPR6 <"` RESERVED2 <" ICPRF <"` RESERVED3 <" IABRV <" RESERVED4 <"IP  <" RESERVED5P "STIR NVIC_TypePNVIC_STIR_INTID_PoslPNVIC_STIR_INTID_Msks8 Q "CPUID "ICSR "VTOR "AIRCR "SCRJ "CCRZ <" SHP  "SHCSR "CFSR "HFSR "DFSR "MMFAR "BFAR "AFSR <"PFR "DFRV "ADR[ <"MMFR <"ISAR <" RESERVED0T "CPACR SCB_Type"PSCB_CPUID_IMPLEMENTER_Pos"PSCB_CPUID_IMPLEMENTER_MskPSCB_CPUID_VARIANT_PosPSCB_CPUID_VARIANT_Msk#PSCB_CPUID_ARCHITECTURE_Posx#PSCB_CPUID_ARCHITECTURE_MskPSCB_CPUID_PARTNO_Pos3PSCB_CPUID_PARTNO_Msk:PSCB_CPUID_REVISION_PosPSCB_CPUID_REVISION_Msk PSCB_ICSR_NMIPENDSET_PosN PSCB_ICSR_NMIPENDSET_MskUPSCB_ICSR_PENDSVSET_PosPSCB_ICSR_PENDSVSET_MskPSCB_ICSR_PENDSVCLR_PosPSCB_ICSR_PENDSVCLR_MskPSCB_ICSR_PENDSTSET_PosPSCB_ICSR_PENDSTSET_MskPSCB_ICSR_PENDSTCLR_PosPSCB_ICSR_PENDSTCLR_Msk PSCB_ICSR_ISRPREEMPT_Pos: PSCB_ICSR_ISRPREEMPT_MskA PSCB_ICSR_ISRPENDING_PosR PSCB_ICSR_ISRPENDING_MskY!PSCB_ICSR_VECTPENDING_Pos !PSCB_ICSR_VECTPENDING_MskPSCB_ICSR_RETTOBASE_PosPSCB_ICSR_RETTOBASE_Msk PSCB_ICSR_VECTACTIVE_PosW PSCB_ICSR_VECTACTIVE_Msk^PSCB_VTOR_TBLBASE_Pos4PSCB_VTOR_TBLBASE_Msk;PSCB_VTOR_TBLOFF_PosvPSCB_VTOR_TBLOFF_Msk}PSCB_AIRCR_VECTKEY_PosPSCB_AIRCR_VECTKEY_Msk"PSCB_AIRCR_VECTKEYSTAT_Pos"PSCB_AIRCR_VECTKEYSTAT_Msk PSCB_AIRCR_ENDIANESS_Posk PSCB_AIRCR_ENDIANESS_MskrPSCB_AIRCR_PRIGROUP_PosPSCB_AIRCR_PRIGROUP_Msk"PSCB_AIRCR_SYSRESETREQ_Pos"PSCB_AIRCR_SYSRESETREQ_Msk$PSCB_AIRCR_VECTCLRACTIVE_Pos.$PSCB_AIRCR_VECTCLRACTIVE_Msk5 PSCB_AIRCR_VECTRESET_PosP PSCB_AIRCR_VECTRESET_MskWPSCB_SCR_SEVONPEND_PosPSCB_SCR_SEVONPEND_MskPSCB_SCR_SLEEPDEEP_PosPSCB_SCR_SLEEPDEEP_Msk PSCB_SCR_SLEEPONEXIT_Pos> PSCB_SCR_SLEEPONEXIT_MskEPSCB_CCR_STKALIGN_PosGPSCB_CCR_STKALIGN_MskNPSCB_CCR_BFHFNMIGN_PosPSCB_CCR_BFHFNMIGN_MskPSCB_CCR_DIV_0_TRP_PosPSCB_CCR_DIV_0_TRP_Msk PSCB_CCR_UNALIGN_TRP_Pos; PSCB_CCR_UNALIGN_TRP_MskB!PSCB_CCR_USERSETMPEND_Pos!PSCB_CCR_USERSETMPEND_Msk#PSCB_CCR_NONBASETHRDENA_Pos#PSCB_CCR_NONBASETHRDENA_Msk"PSCB_SHCSR_USGFAULTENA_Pos"PSCB_SHCSR_USGFAULTENA_Msk"PSCB_SHCSR_BUSFAULTENA_Pos"PSCB_SHCSR_BUSFAULTENA_Msk"PSCB_SHCSR_MEMFAULTENA_Pos"PSCB_SHCSR_MEMFAULTENA_Msk#PSCB_SHCSR_SVCALLPENDED_Posx#PSCB_SHCSR_SVCALLPENDED_Msk%PSCB_SHCSR_BUSFAULTPENDED_Pos%PSCB_SHCSR_BUSFAULTPENDED_Msk%PSCB_SHCSR_MEMFAULTPENDED_Pos%PSCB_SHCSR_MEMFAULTPENDED_Msk%PSCB_SHCSR_USGFAULTPENDED_Pos%PSCB_SHCSR_USGFAULTPENDED_Msk!PSCB_SHCSR_SYSTICKACT_Pos!PSCB_SHCSR_SYSTICKACT_Msk PSCB_SHCSR_PENDSVACT_PosK PSCB_SHCSR_PENDSVACT_MskR!PSCB_SHCSR_MONITORACT_Pos!PSCB_SHCSR_MONITORACT_Msk PSCB_SHCSR_SVCALLACT_PosV PSCB_SHCSR_SVCALLACT_Msk]"PSCB_SHCSR_USGFAULTACT_Pos"PSCB_SHCSR_USGFAULTACT_Msk"PSCB_SHCSR_BUSFAULTACT_Pos"PSCB_SHCSR_BUSFAULTACT_Msk"PSCB_SHCSR_MEMFAULTACT_Pos"PSCB_SHCSR_MEMFAULTACT_Msk PSCB_CFSR_USGFAULTSR_Pos8 PSCB_CFSR_USGFAULTSR_Msk? PSCB_CFSR_BUSFAULTSR_Pos= PSCB_CFSR_BUSFAULTSR_MskD PSCB_CFSR_MEMFAULTSR_PosH PSCB_CFSR_MEMFAULTSR_MskOPSCB_CFSR_MMARVALID_PosPSCB_CFSR_MMARVALID_MskPSCB_CFSR_MSTKERR_Pos&PSCB_CFSR_MSTKERR_Msk-PSCB_CFSR_MUNSTKERR_PosPSCB_CFSR_MUNSTKERR_MskPSCB_CFSR_DACCVIOL_PosPSCB_CFSR_DACCVIOL_MskPSCB_CFSR_IACCVIOL_PosPSCB_CFSR_IACCVIOL_Msk PSCB_CFSR_BFARVALID_PosPSCB_CFSR_BFARVALID_MskPSCB_CFSR_STKERR_PosuPSCB_CFSR_STKERR_Msk|PSCB_CFSR_UNSTKERR_PosPSCB_CFSR_UNSTKERR_Msk!PSCB_CFSR_IMPRECISERR_Pos!PSCB_CFSR_IMPRECISERR_MskPSCB_CFSR_PRECISERR_PosPSCB_CFSR_PRECISERR_MskPSCB_CFSR_IBUSERR_Pos2PSCB_CFSR_IBUSERR_Msk9PSCB_CFSR_DIVBYZERO_PosPSCB_CFSR_DIVBYZERO_MskPSCB_CFSR_UNALIGNED_PosPSCB_CFSR_UNALIGNED_MskPSCB_CFSR_NOCP_Pos$PSCB_CFSR_NOCP_Msk+PSCB_CFSR_INVPC_PosPSCB_CFSR_INVPC_MskPSCB_CFSR_INVSTATE_PosPSCB_CFSR_INVSTATE_Msk PSCB_CFSR_UNDEFINSTR_PosF PSCB_CFSR_UNDEFINSTR_MskMPSCB_HFSR_DEBUGEVT_PosPSCB_HFSR_DEBUGEVT_MskPSCB_HFSR_FORCED_PosPSCB_HFSR_FORCED_MskPSCB_HFSR_VECTTBL_Pos5PSCB_HFSR_VECTTBL_Msk<PSCB_DFSR_EXTERNAL_PosPSCB_DFSR_EXTERNAL_MskPSCB_DFSR_VCATCH_PosPSCB_DFSR_VCATCH_MskPSCB_DFSR_DWTTRAP_Pos'PSCB_DFSR_DWTTRAP_Msk.PSCB_DFSR_BKPT_Pos"PSCB_DFSR_BKPT_Msk)PSCB_DFSR_HALTED_PosPSCB_DFSR_HALTED_Msk8 Q <" RESERVED06 "ICTR "ACTLR SCnSCB_Type$PSCnSCB_ICTR_INTLINESNUM_Pos$PSCnSCB_ICTR_INTLINESNUM_Msk!PSCnSCB_ACTLR_DISFOLD_Pos!PSCnSCB_ACTLR_DISFOLD_Msk$PSCnSCB_ACTLR_DISDEFWBUF_Pos$PSCnSCB_ACTLR_DISDEFWBUF_Msk$PSCnSCB_ACTLR_DISMCYCINT_Pos$PSCnSCB_ACTLR_DISMCYCINT_Msk8 Q "CTRL "LOAD "VAL "CALIB SysTick_Type#PSysTick_CTRL_COUNTFLAG_Pos#PSysTick_CTRL_COUNTFLAG_Msk#PSysTick_CTRL_CLKSOURCE_Pos#PSysTick_CTRL_CLKSOURCE_Msk!PSysTick_CTRL_TICKINT_Pos7!PSysTick_CTRL_TICKINT_Msk> PSysTick_CTRL_ENABLE_Pos PSysTick_CTRL_ENABLE_Msk PSysTick_LOAD_RELOAD_Pos PSysTick_LOAD_RELOAD_Msk PSysTick_VAL_CURRENT_Pos~ PSysTick_VAL_CURRENT_Msk PSysTick_CALIB_NOREF_Pos PSysTick_CALIB_NOREF_MskPSysTick_CALIB_SKEW_PosPSysTick_CALIB_SKEW_Msk PSysTick_CALIB_TENMS_Pos PSysTick_CALIB_TENMS_Msk8 Q8 S "u8: "u16 "u32 <"PORT <" RESERVED0y "TER <"< RESERVED1 "TPR <"< RESERVED2 "TCR <"t RESERVED3 "IWR "IRR "IMCR <" RESERVED4c "LAR "LSR <" RESERVED5 "PID4 "PID5 "PID6 "PID7 "PID0 "PID1 "PID2 "PID3 "CID0 "CID1 "CID2 "CID3 ITM_TypePITM_TPR_PRIVMASK_PosPITM_TPR_PRIVMASK_MskPITM_TCR_BUSY_PosFPITM_TCR_BUSY_MskMPITM_TCR_TraceBusID_PosPITM_TCR_TraceBusID_MskPITM_TCR_GTSFREQ_PosgPITM_TCR_GTSFREQ_MsknPITM_TCR_TSPrescale_PosPITM_TCR_TSPrescale_MskPITM_TCR_SWOENA_PosPITM_TCR_SWOENA_MskPITM_TCR_DWTENA_PosPITM_TCR_DWTENA_MskPITM_TCR_SYNCENA_PosrPITM_TCR_SYNCENA_MskyPITM_TCR_TSENA_Pos PITM_TCR_TSENA_MskPITM_TCR_ITMENA_PosPITM_TCR_ITMENA_MskPITM_IWR_ATVALIDM_Pos&PITM_IWR_ATVALIDM_Msk-PITM_IRR_ATREADYM_Pos&PITM_IRR_ATREADYM_Msk-!PITM_IMCR_INTEGRATION_Pos!PITM_IMCR_INTEGRATION_MskPITM_LSR_ByteAcc_PosPITM_LSR_ByteAcc_MskPITM_LSR_Access_Pos+PITM_LSR_Access_Msk2PITM_LSR_Present_PosPITM_LSR_Present_Msk8 Q "CTRL "CYCCNTS "CPICNTV "EXCCNTR " SLEEPCNT "LSUCNT> "FOLDCNT  "PCSR "COMP0 "MASK0 " FUNCTION0{ <" RESERVED0O "COMP1 "MASK1 " FUNCTION1z <" RESERVED1N "COMP2 "MASK2 " FUNCTION2y <" RESERVED2M "COMP3 "MASK3 " FUNCTION3x DWT_TypePDWT_CTRL_NUMCOMP_PosPDWT_CTRL_NUMCOMP_MskPDWT_CTRL_NOTRCPKT_PosPDWT_CTRL_NOTRCPKT_MskPDWT_CTRL_NOEXTTRIG_PoshPDWT_CTRL_NOEXTTRIG_MskoPDWT_CTRL_NOCYCCNT_PosPDWT_CTRL_NOCYCCNT_MskPDWT_CTRL_NOPRFCNT_PosPDWT_CTRL_NOPRFCNT_MskPDWT_CTRL_CYCEVTENA_PosPDWT_CTRL_CYCEVTENA_Msk PDWT_CTRL_FOLDEVTENA_PosB PDWT_CTRL_FOLDEVTENA_MskIPDWT_CTRL_LSUEVTENA_PosuPDWT_CTRL_LSUEVTENA_Msk|!PDWT_CTRL_SLEEPEVTENA_Pos!PDWT_CTRL_SLEEPEVTENA_MskPDWT_CTRL_EXCEVTENA_PosPDWT_CTRL_EXCEVTENA_MskPDWT_CTRL_CPIEVTENA_PosPDWT_CTRL_CPIEVTENA_MskPDWT_CTRL_EXCTRCENA_PosPDWT_CTRL_EXCTRCENA_Msk PDWT_CTRL_PCSAMPLENA_PosF PDWT_CTRL_PCSAMPLENA_MskMPDWT_CTRL_SYNCTAP_PosPDWT_CTRL_SYNCTAP_MskPDWT_CTRL_CYCTAP_PosnPDWT_CTRL_CYCTAP_MskuPDWT_CTRL_POSTINIT_PosPDWT_CTRL_POSTINIT_Msk PDWT_CTRL_POSTPRESET_Pos PDWT_CTRL_POSTPRESET_MskPDWT_CTRL_CYCCNTENA_PosPDWT_CTRL_CYCCNTENA_MskPDWT_CPICNT_CPICNT_PosPDWT_CPICNT_CPICNT_MskPDWT_EXCCNT_EXCCNT_PosPDWT_EXCCNT_EXCCNT_Msk"PDWT_SLEEPCNT_SLEEPCNT_Pos"PDWT_SLEEPCNT_SLEEPCNT_MskPDWT_LSUCNT_LSUCNT_PosPDWT_LSUCNT_LSUCNT_Msk PDWT_FOLDCNT_FOLDCNT_PosK PDWT_FOLDCNT_FOLDCNT_MskRPDWT_MASK_MASK_PosPDWT_MASK_MASK_Msk!PDWT_FUNCTION_MATCHED_Pos!PDWT_FUNCTION_MATCHED_Msk$PDWT_FUNCTION_DATAVADDR1_Pos5$PDWT_FUNCTION_DATAVADDR1_Msk<$PDWT_FUNCTION_DATAVADDR0_Pos6$PDWT_FUNCTION_DATAVADDR0_Msk=#PDWT_FUNCTION_DATAVSIZE_PosH#PDWT_FUNCTION_DATAVSIZE_MskO!PDWT_FUNCTION_LNK1ENA_Pos !PDWT_FUNCTION_LNK1ENA_Msk$PDWT_FUNCTION_DATAVMATCH_Pos$PDWT_FUNCTION_DATAVMATCH_Msk"PDWT_FUNCTION_CYCMATCH_Pos"PDWT_FUNCTION_CYCMATCH_Msk#PDWT_FUNCTION_EMITRANGE_PosW#PDWT_FUNCTION_EMITRANGE_Msk^"PDWT_FUNCTION_FUNCTION_Pos"PDWT_FUNCTION_FUNCTION_Msk8 Q "SSPSR# "CSPSR3 <" RESERVED0 "ACPR <" RESERVED1 "SPPR{ <" RESERVED2e "FFSR "FFCR "FSCR <" RESERVED3 "TRIGGER "FIFO0j " ITATBCTR2' <" RESERVED4 " ITATBCTR0) "FIFO1i "ITCTRL <" RESERVED5U " CLAIMSETf " CLAIMCLRq <"  RESERVED7 "DEVIDR "DEVTYPE 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PTPI_DEVID_MANCVALID_Posf PTPI_DEVID_MANCVALID_Mskm PTPI_DEVID_PTINVALID_PosJ PTPI_DEVID_PTINVALID_MskQPTPI_DEVID_MinBufSz_PosPTPI_DEVID_MinBufSz_Msk PTPI_DEVID_AsynClkIn_Pos PTPI_DEVID_AsynClkIn_Msk#PTPI_DEVID_NrTraceInput_Pos0#PTPI_DEVID_NrTraceInput_Msk7 PTPI_DEVTYPE_SubType_Post PTPI_DEVTYPE_SubType_Msk{"PTPI_DEVTYPE_MajorType_Pos"PTPI_DEVTYPE_MajorType_Msk8 Q "DHCSRg "DCRSR] "DCRDRl "DEMCRpCoreDebug_Typet#PCoreDebug_DHCSR_DBGKEY_Pos#PCoreDebug_DHCSR_DBGKEY_Msk'PCoreDebug_DHCSR_S_RESET_ST_Pos!'PCoreDebug_DHCSR_S_RESET_ST_Msk((P CoreDebug_DHCSR_S_RETIRE_ST_Pos(P CoreDebug_DHCSR_S_RETIRE_ST_Msk%PCoreDebug_DHCSR_S_LOCKUP_Pos%PCoreDebug_DHCSR_S_LOCKUP_Msk$PCoreDebug_DHCSR_S_SLEEP_Pos7$PCoreDebug_DHCSR_S_SLEEP_Msk>#PCoreDebug_DHCSR_S_HALT_Pos#PCoreDebug_DHCSR_S_HALT_Msk%PCoreDebug_DHCSR_S_REGRDY_Pos%PCoreDebug_DHCSR_S_REGRDY_Msk(P CoreDebug_DHCSR_C_SNAPSTALL_Pos(P CoreDebug_DHCSR_C_SNAPSTALL_Msk 'PCoreDebug_DHCSR_C_MASKINTS_PosP'PCoreDebug_DHCSR_C_MASKINTS_MskW#PCoreDebug_DHCSR_C_STEP_Pos#PCoreDebug_DHCSR_C_STEP_Msk#PCoreDebug_DHCSR_C_HALT_Pos#PCoreDebug_DHCSR_C_HALT_Msk&PCoreDebug_DHCSR_C_DEBUGEN_Pos&PCoreDebug_DHCSR_C_DEBUGEN_Msk#PCoreDebug_DCRSR_REGWnR_Pose#PCoreDebug_DCRSR_REGWnR_Mskl#PCoreDebug_DCRSR_REGSEL_Pos#PCoreDebug_DCRSR_REGSEL_Msk#PCoreDebug_DEMCR_TRCENA_Pos#PCoreDebug_DEMCR_TRCENA_Msk$PCoreDebug_DEMCR_MON_REQ_Pos:$PCoreDebug_DEMCR_MON_REQ_MskA%PCoreDebug_DEMCR_MON_STEP_Pos%PCoreDebug_DEMCR_MON_STEP_Msk%PCoreDebug_DEMCR_MON_PEND_Pos%PCoreDebug_DEMCR_MON_PEND_Msk#PCoreDebug_DEMCR_MON_EN_Pos#PCoreDebug_DEMCR_MON_EN_Msk'PCoreDebug_DEMCR_VC_HARDERR_Pose'PCoreDebug_DEMCR_VC_HARDERR_Mskl&PCoreDebug_DEMCR_VC_INTERR_Pos&PCoreDebug_DEMCR_VC_INTERR_Msk&PCoreDebug_DEMCR_VC_BUSERR_Pos&PCoreDebug_DEMCR_VC_BUSERR_Msk'PCoreDebug_DEMCR_VC_STATERR_PosH'PCoreDebug_DEMCR_VC_STATERR_MskO&PCoreDebug_DEMCR_VC_CHKERR_Pos&PCoreDebug_DEMCR_VC_CHKERR_Msk'PCoreDebug_DEMCR_VC_NOCPERR_PosT'PCoreDebug_DEMCR_VC_NOCPERR_Msk[%PCoreDebug_DEMCR_VC_MMERR_Pos%PCoreDebug_DEMCR_VC_MMERR_Msk)P!CoreDebug_DEMCR_VC_CORERESET_Pos)P!CoreDebug_DEMCR_VC_CORERESET_MskP _VAL2FLDqP _FLD2VALqP SCS_BASEXP ITM_BASEWP DWT_BASERP TPI_BASETPCoreDebug_BASEP SysTick_BASEoP NVIC_BASEP SCB_BASEiPSCnSCB PSCBPSysTick PNVIC PITM PDWT PTPIP CoreDebugIPCMSIS_NVIC_VIRTUAL!PNVIC_SetPriorityGrouping3!PNVIC_GetPriorityGrouping?PNVIC_EnableIRQPNVIC_GetEnableIRQPNVIC_DisableIRQ~PNVIC_GetPendingIRQGPNVIC_SetPendingIRQ;PNVIC_ClearPendingIRQ|PNVIC_GetActivePNVIC_SetPriorityPNVIC_GetPriorityPNVIC_SystemResetPCMSIS_VECTAB_VIRTUALPNVIC_SetVectorPNVIC_GetVectorPNVIC_USER_IRQ_OFFSETdPEXC_RETURN_HANDLER+PEXC_RETURN_THREAD_MSPPEXC_RETURN_THREAD_PSP#__NVIC_SetPriorityGrouping, "PriorityGroupm " reg_valueN "PriorityGroupTmpZ#__NVIC_GetPriorityGrouping__NVIC_EnableIRQT,""IRQnz__NVIC_GetEnableIRQ.,""IRQnx__NVIC_DisableIRQ,""IRQnv__schedule_barriers__dsb__isb__NVIC_GetPendingIRQ,""IRQnq__NVIC_SetPendingIRQ,""IRQno__NVIC_ClearPendingIRQ,""IRQnm__NVIC_GetActive ,""IRQnk__NVIC_SetPriority,""IRQni, " priorityN__NVIC_GetPriority,""IRQnfNVIC_EncodePriority, "PriorityGroupR, "PreemptPriority~, " SubPriority9 "PriorityGroupTmp? "PreemptPriorityBits "SubPriorityBitsNVIC_DecodePriority, " Priorityb, "PriorityGroupK,"pPreemptPriority," pSubPriority "PriorityGroupTmp8 "PreemptPriorityBits "SubPriorityBits__NVIC_SetVector,""IRQnU, "vector-"vectors__NVIC_GetVector,""IRQnQ"vectors__NVIC_SystemReset__nopSCB_GetFPUTypeSysTick_ConfigY, "ticks ITM_RxBufferxPITM_RXBUFFER_EMPTY  ITM_SendChar , "chITM_ReceiveCharL "chITM_CheckChar5P__SYSTEM_STM32F10X_H SystemCoreClock<AHBPrescTable<APBPrescTable SystemInitSystemCoreClockUpdatea8 Q "SR "CR1r "CR2q "SMPR1 "SMPR2 "JOFR1 "JOFR2 "JOFR3 "JOFR4 "HTRJ "LTRF "SQR1 "SQR2 "SQR3  "JSQR "JDR1% "JDR2$ "JDR3# "JDR4" "DR ADC_TypeDef8 Q "SR "CR1\ "CR2[ <"@ RESERVEDJ "DRADC_Common_TypeDef=8 Q " RESERVED0 "DR1T "DR2S "DR3R "DR4Q "DR5P "DR6O "DR7N "DR8M "DR9L "DR10" "RTCCR "CR "CSR3 <" RESERVED13 "DR11! "DR12  "DR13 "DR14 "DR15 "DR16 "DR17 "DR18 "DR19 "DR20! "DR21  "DR22 "DR23 "DR24 "DR25 "DR26 "DR27 "DR28 "DR29 "DR30  "DR31 "DR32 "DR33 "DR34 "DR35 "DR36 "DR37 "DR38 "DR39 "DR40 "DR41 "DR42 BKP_TypeDef8 Q "TIR "TDTR "TDLR "TDHRCAN_TxMailBox_TypeDef8 Q "RIR "RDTR "RDLR "RDHR CAN_FIFOMailBox_TypeDef8 Q "FR1 "FR2#CAN_FilterRegister_TypeDef8 Q "MCR "MSR "TSR "RF0R "RF1R "IER "ESR "BTR <" RESERVED0- <"0 sTxMailBox <"  sFIFOMailBox7 <"0 RESERVED1 "FMR "FM1R " RESERVED2< "FS1R " RESERVED3; "FFA1R " RESERVED4: "FA1R <"  RESERVED5 <"psFilterRegister CAN_TypeDef 8 Q "DR. "IDR " RESERVED0- " RESERVED1# "CR/ CRC_TypeDef8 Q " CR " SWTRIGR " DHR12R1n " DHR12L1t " DHR8R1 " DHR12R2m " DHR12L2s " DHR8R2 " DHR12RD[ " DHR12LDa " DHR8RD " DOR1" " DOR2! DAC_TypeDef8 Q " IDCODE} " CRDBGMCU_TypeDef#8 Q " CCRO " CNDTR " CPAR " CMARDMA_Channel_TypeDef8 Q " ISR3 " IFCR DMA_TypeDef 8 Q " IMR5 " EMR9 " RTSR " FTSR " SWIER " PR} EXTI_TypeDef8 Q " ACR? " KEYR " OPTKEYR " SRr " CR " AR " RESERVED " OBR2 " WRPRFLASH_TypeDefi8 Q " RDP" " USER " Data0Z " Data1Y " WRP0 " WRP1 " WRP2 " WRP3 OB_TypeDefL8 Q <" BTCRFSMC_Bank1_TypeDef8 Q <" BWTRrFSMC_Bank1E_TypeDefQ8 Q " PCR2 " SR2# " PMEM2 " PATT2 " RESERVED0^ " ECCR2 " RESERVED1] " RESERVED2\ " PCR3 " SR3" " PMEM3 " PATT3 " RESERVED3[ " ECCR3FSMC_Bank2_3_TypeDef8 Q " PCR4 " SR4 " PMEM4 " PATT4y " PIO4FSMC_Bank4_TypeDef8 Q " CRL " CRH " IDR " ODR " BSRR " BRR " LCKR GPIO_TypeDef8 Q " EVCR " MAPR <" EXTICR " RESERVED0> " MAPR2t AFIO_TypeDef8 Q " CR1  " CR2  " OAR1 " OAR2 " DR? " SR1 " SR2 " CCR " TRISEH I2C_TypeDef8 Q " KR- " PR( " RLR " SR% IWDG_TypeDef8 Q " CR/ " CSR PWR_TypeDef8 Q " CR+ " CFGR " CIR " APB2RSTRd " APB1RSTRe " AHBENR " APB2ENR " APB1ENR " BDCR " CSR RCC_TypeDef8 Q " CRHT " CRLP " PRLH " PRLL " DIVH " DIVL " CNTH " CNTL " ALRH " ALRL RTC_TypeDef8 Q " POWER " CLKCR " ARGK " CMDQ " RESPCMD " RESP1 " RESP2 " RESP3 " RESP4 " DTIMERZ " DLEN " DCTRL " DCOUNTR " STA= " ICRG " MASK <" RESERVED0S " FIFOCNT <"4 RESERVED1& " FIFO SDIO_TypeDef8 Q " CR1I " CR2H " SRl " DR{ " CRCPR " RXCRCR5 " TXCRCR3 " I2SCFGR " I2SPR SPI_TypeDef8 Q " CR1> " CR2= " SMCR " DIER " SRa " EGR& " CCMR1 " CCMR2 " CCER " CNT " PSC " ARR " RCR " CCR1 " CCR2 " CCR3 " CCR4 " BDTR " DCR+ " DMAR " ORe TIM_TypeDef8 Q " SRJ " DRY " BRR " CR1' " CR2& " CR3% " GTPRUSART_TypeDefH8 Q " EP0R " RESERVED0F " EP1R " RESERVED1E " EP2R " RESERVED2D " EP3R " RESERVED3C " EP4R " RESERVED4B " EP5R " RESERVED5A " EP6R " RESERVED6@ " EP7R <"" RESERVED7 " CNTR " RESERVED8> " ISTR " RESERVED9= " FNR " RESERVEDA5 " DADDR " RESERVEDB4 " BTABLE2 " RESERVEDC3 USB_TypeDef8 Q " CR5 " CFR " SR% WWDG_TypeDefP FLASH_BASEPFLASH_BANK1_END]P SRAM_BASE P PERIPH_BASEsP SRAM_BB_BASE#PPERIPH_BB_BASEP FSMC_BASEP FSMC_R_BASEaPAPB1PERIPH_BASEgPAPB2PERIPH_BASEfPAHBPERIPH_BASEP TIM2_BASE#P TIM3_BASE"P TIM4_BASE!P TIM5_BASE P TIM6_BASEP TIM7_BASEP RTC_BASEXP WWDG_BASEP IWDG_BASEP SPI2_BASE!P SPI3_BASE P USART2_BASEzP USART3_BASEyP UART4_BASEP UART5_BASEP I2C1_BASEPP I2C2_BASEOP CAN1_BASE<P BKP_BASEdP PWR_BASEHP DAC_BASEyP AFIO_BASE P EXTI_BASEP GPIOA_BASEP GPIOB_BASEP GPIOC_BASEP GPIOD_BASEP GPIOE_BASEP GPIOF_BASEP GPIOG_BASEP ADC1_BASEFP ADC2_BASEEP TIM1_BASE$P SPI1_BASE"P TIM8_BASEP USART1_BASE{P ADC3_BASEDP SDIO_BASEP DMA1_BASE<PDMA1_Channel1_BASEPDMA1_Channel2_BASEPDMA1_Channel3_BASEPDMA1_Channel4_BASEPDMA1_Channel5_BASEPDMA1_Channel6_BASEPDMA1_Channel7_BASEP DMA2_BASE;PDMA2_Channel1_BASEPDMA2_Channel2_BASEPDMA2_Channel3_BASEPDMA2_Channel4_BASEPDMA2_Channel5_BASEP RCC_BASEiP CRC_BASEiP FLASH_R_BASEPFLASHSIZE_BASEP UID_BASE_POB_BASEP FSMC_BANK1P FSMC_BANK1_1NP FSMC_BANK1_2MP FSMC_BANK1_3LP FSMC_BANK1_4KP FSMC_BANK2P FSMC_BANK3P FSMC_BANK4PFSMC_BANK1_R_BASEPFSMC_BANK1E_R_BASEbPFSMC_BANK2_3_R_BASEPFSMC_BANK4_R_BASEP DBGMCU_BASEP USB_BASEWP USB_PMAADDRs PTIM2 PTIM3 PTIM4 PTIM5 PTIM6 PTIM7 PRTC PWWDG PIWDG PSPI2 PSPI3PUSART2PUSART3PUART4QPUART5P PI2C1 PI2C2 PUSB PCAN1 PBKP PPWR PDAC1 PDAC PAFIO PEXTIPGPIOAQPGPIOBPPGPIOCOPGPIODNPGPIOEMPGPIOFLPGPIOGK PADC1 PADC2 PADC3P ADC12_COMMON` PTIM1 PSPI1 PTIM8PUSART1 PSDIO PDMA1 PDMA2PDMA1_Channel1ePDMA1_Channel2dPDMA1_Channel3cPDMA1_Channel4bPDMA1_Channel5aPDMA1_Channel6`PDMA1_Channel7_PDMA2_Channel1dPDMA2_Channel2cPDMA2_Channel3bPDMA2_Channel4aPDMA2_Channel5` PRCC PCRCPFLASHS POB6P FSMC_Bank1P FSMC_Bank1E;P FSMC_Bank2_3P FSMC_Bank4PDBGMCU PCRC_DR_DR_Pos^PCRC_DR_DR_MskeP CRC_DR_DRPCRC_IDR_IDR_PosPCRC_IDR_IDR_MskP CRC_IDR_IDRaPCRC_CR_RESET_PoslPCRC_CR_RESET_MsksP CRC_CR_RESETPPWR_CR_LPDS_PosPPWR_CR_LPDS_MskP PWR_CR_LPDS6PPWR_CR_PDDS_PosPPWR_CR_PDDS_MskP PWR_CR_PDDS>PPWR_CR_CWUF_PosPPWR_CR_CWUF_MskP PWR_CR_CWUF4PPWR_CR_CSBF_PosPPWR_CR_CSBF_MskP PWR_CR_CSBFKPPWR_CR_PVDE_PosPPWR_CR_PVDE_MskP PWR_CR_PVDE:PPWR_CR_PLS_PosPPWR_CR_PLS_MskP PWR_CR_PLS|P PWR_CR_PLS_0P PWR_CR_PLS_1P PWR_CR_PLS_2PPWR_CR_PLS_LEV0PPWR_CR_PLS_LEV1PPWR_CR_PLS_LEV2PPWR_CR_PLS_LEV3PPWR_CR_PLS_LEV4PPWR_CR_PLS_LEV5PPWR_CR_PLS_LEV6PPWR_CR_PLS_LEV7PPWR_CR_PLS_2V2[PPWR_CR_PLS_2V3ZPPWR_CR_PLS_2V4YPPWR_CR_PLS_2V5XPPWR_CR_PLS_2V6WPPWR_CR_PLS_2V7VPPWR_CR_PLS_2V8UPPWR_CR_PLS_2V9TPPWR_CR_DBP_PosPPWR_CR_DBP_MskP PWR_CR_DBPPPWR_CSR_WUF_PosPPWR_CSR_WUF_MskP PWR_CSR_WUF$PPWR_CSR_SBF_PosPPWR_CSR_SBF_MskP PWR_CSR_SBF;PPWR_CSR_PVDO_PosBPPWR_CSR_PVDO_MskIP PWR_CSR_PVDOPPWR_CSR_EWUP_Pos:PPWR_CSR_EWUP_MskAP PWR_CSR_EWUPPBKP_DR1_D_PoszPBKP_DR1_D_MskP BKP_DR1_DPBKP_DR2_D_PosyPBKP_DR2_D_MskP BKP_DR2_DPBKP_DR3_D_PosxPBKP_DR3_D_MskP BKP_DR3_DPBKP_DR4_D_PoswPBKP_DR4_D_Msk~P BKP_DR4_DPBKP_DR5_D_PosvPBKP_DR5_D_Msk}P BKP_DR5_DPBKP_DR6_D_PosuPBKP_DR6_D_Msk|P BKP_DR6_DPBKP_DR7_D_PostPBKP_DR7_D_Msk{P BKP_DR7_D PBKP_DR8_D_PossPBKP_DR8_D_MskzP BKP_DR8_D PBKP_DR9_D_PosrPBKP_DR9_D_MskyP BKP_DR9_D PBKP_DR10_D_PosHPBKP_DR10_D_MskOP BKP_DR10_DPBKP_DR11_D_PosGPBKP_DR11_D_MskNP BKP_DR11_DPBKP_DR12_D_PosFPBKP_DR12_D_MskMP BKP_DR12_DPBKP_DR13_D_PosEPBKP_DR13_D_MskLP BKP_DR13_DPBKP_DR14_D_PosDPBKP_DR14_D_MskKP BKP_DR14_DPBKP_DR15_D_PosCPBKP_DR15_D_MskJP BKP_DR15_DPBKP_DR16_D_PosBPBKP_DR16_D_MskIP BKP_DR16_DPBKP_DR17_D_PosAPBKP_DR17_D_MskHP BKP_DR17_DPBKP_DR18_D_Pos@PBKP_DR18_D_MskGP BKP_DR18_DPBKP_DR19_D_Pos?PBKP_DR19_D_MskFP BKP_DR19_DPBKP_DR20_D_PosGPBKP_DR20_D_MskNP BKP_DR20_DPBKP_DR21_D_PosFPBKP_DR21_D_MskMP BKP_DR21_DPBKP_DR22_D_PosEPBKP_DR22_D_MskLP BKP_DR22_DPBKP_DR23_D_PosDPBKP_DR23_D_MskKP BKP_DR23_DPBKP_DR24_D_PosCPBKP_DR24_D_MskJP BKP_DR24_DPBKP_DR25_D_PosBPBKP_DR25_D_MskIP BKP_DR25_DPBKP_DR26_D_PosAPBKP_DR26_D_MskHP BKP_DR26_DPBKP_DR27_D_Pos@PBKP_DR27_D_MskGP BKP_DR27_DPBKP_DR28_D_Pos?PBKP_DR28_D_MskFP BKP_DR28_DPBKP_DR29_D_Pos>PBKP_DR29_D_MskEP BKP_DR29_DPBKP_DR30_D_PosFPBKP_DR30_D_MskMP BKP_DR30_DPBKP_DR31_D_PosEPBKP_DR31_D_MskLP BKP_DR31_DPBKP_DR32_D_PosDPBKP_DR32_D_MskKP BKP_DR32_DPBKP_DR33_D_PosCPBKP_DR33_D_MskJP BKP_DR33_DPBKP_DR34_D_PosBPBKP_DR34_D_MskIP BKP_DR34_DPBKP_DR35_D_PosAPBKP_DR35_D_MskHP BKP_DR35_DPBKP_DR36_D_Pos@PBKP_DR36_D_MskGP BKP_DR36_DPBKP_DR37_D_Pos?PBKP_DR37_D_MskFP BKP_DR37_DPBKP_DR38_D_Pos>PBKP_DR38_D_MskEP BKP_DR38_DPBKP_DR39_D_Pos=PBKP_DR39_D_MskDP BKP_DR39_DPBKP_DR40_D_PosEPBKP_DR40_D_MskLP BKP_DR40_DPBKP_DR41_D_PosDPBKP_DR41_D_MskKP BKP_DR41_DPBKP_DR42_D_PosCPBKP_DR42_D_MskJP BKP_DR42_DPRTC_BKP_NUMBERbPBKP_RTCCR_CAL_Pos/PBKP_RTCCR_CAL_Msk6PBKP_RTCCR_CALPBKP_RTCCR_CCO_Pos*PBKP_RTCCR_CCO_Msk1PBKP_RTCCR_CCOPBKP_RTCCR_ASOE_PosPBKP_RTCCR_ASOE_MskPBKP_RTCCR_ASOEnPBKP_RTCCR_ASOS_PosPBKP_RTCCR_ASOS_MskPBKP_RTCCR_ASOS`PBKP_CR_TPE_PosPBKP_CR_TPE_Msk P BKP_CR_TPEPBKP_CR_TPAL_PosPBKP_CR_TPAL_MskP BKP_CR_TPALTPBKP_CSR_CTE_PosPBKP_CSR_CTE_MskP BKP_CSR_CTEVPBKP_CSR_CTI_PosPBKP_CSR_CTI_MskP BKP_CSR_CTIRPBKP_CSR_TPIE_PosePBKP_CSR_TPIE_MsklP BKP_CSR_TPIEPBKP_CSR_TEF_PosPBKP_CSR_TEF_MskP BKP_CSR_TEFSPBKP_CSR_TIF_PosPBKP_CSR_TIF_MskP BKP_CSR_TIFOPRCC_CR_HSION_PosnPRCC_CR_HSION_MskuP RCC_CR_HSIONPRCC_CR_HSIRDY_PosPRCC_CR_HSIRDY_Msk!PRCC_CR_HSIRDYPRCC_CR_HSITRIM_PosPRCC_CR_HSITRIM_MskPRCC_CR_HSITRIMdPRCC_CR_HSICAL_Pos9PRCC_CR_HSICAL_Msk@PRCC_CR_HSICALPRCC_CR_HSEON_PosrPRCC_CR_HSEON_MskyP RCC_CR_HSEON PRCC_CR_HSERDY_PosPRCC_CR_HSERDY_Msk%PRCC_CR_HSERDYPRCC_CR_HSEBYP_Pos"PRCC_CR_HSEBYP_Msk)PRCC_CR_HSEBYPPRCC_CR_CSSON_PosiPRCC_CR_CSSON_MskpP RCC_CR_CSSONPRCC_CR_PLLON_PosjPRCC_CR_PLLON_MskqP RCC_CR_PLLONPRCC_CR_PLLRDY_PosPRCC_CR_PLLRDY_MskPRCC_CR_PLLRDYPRCC_CFGR_SW_PosPRCC_CFGR_SW_MskP RCC_CFGR_SWSPRCC_CFGR_SW_0PRCC_CFGR_SW_1PRCC_CFGR_SW_HSIPRCC_CFGR_SW_HSE PRCC_CFGR_SW_PLLPRCC_CFGR_SWS_PosePRCC_CFGR_SWS_MsklP RCC_CFGR_SWSPRCC_CFGR_SWS_0kPRCC_CFGR_SWS_1jPRCC_CFGR_SWS_HSIPRCC_CFGR_SWS_HSEPRCC_CFGR_SWS_PLLPRCC_CFGR_HPRE_Pos1PRCC_CFGR_HPRE_Msk8PRCC_CFGR_HPREPRCC_CFGR_HPRE_07PRCC_CFGR_HPRE_16PRCC_CFGR_HPRE_25PRCC_CFGR_HPRE_34PRCC_CFGR_HPRE_DIV1MPRCC_CFGR_HPRE_DIV2LPRCC_CFGR_HPRE_DIV4JPRCC_CFGR_HPRE_DIV8FPRCC_CFGR_HPRE_DIV16PRCC_CFGR_HPRE_DIV64PRCC_CFGR_HPRE_DIV128PRCC_CFGR_HPRE_DIV256PRCC_CFGR_HPRE_DIV512PRCC_CFGR_PPRE1_PosPRCC_CFGR_PPRE1_MskPRCC_CFGR_PPRE1PRCC_CFGR_PPRE1_0PRCC_CFGR_PPRE1_1PRCC_CFGR_PPRE1_2PRCC_CFGR_PPRE1_DIV1PRCC_CFGR_PPRE1_DIV2PRCC_CFGR_PPRE1_DIV4PRCC_CFGR_PPRE1_DIV8 PRCC_CFGR_PPRE1_DIV16PRCC_CFGR_PPRE2_PosPRCC_CFGR_PPRE2_MskPRCC_CFGR_PPRE2PRCC_CFGR_PPRE2_0PRCC_CFGR_PPRE2_1PRCC_CFGR_PPRE2_2PRCC_CFGR_PPRE2_DIV1PRCC_CFGR_PPRE2_DIV2PRCC_CFGR_PPRE2_DIV4PRCC_CFGR_PPRE2_DIV8 PRCC_CFGR_PPRE2_DIV16PRCC_CFGR_ADCPRE_PosPRCC_CFGR_ADCPRE_MskPRCC_CFGR_ADCPREFPRCC_CFGR_ADCPRE_0PRCC_CFGR_ADCPRE_1PRCC_CFGR_ADCPRE_DIV2PRCC_CFGR_ADCPRE_DIV4PRCC_CFGR_ADCPRE_DIV6PRCC_CFGR_ADCPRE_DIV8PRCC_CFGR_PLLSRC_PosPRCC_CFGR_PLLSRC_MskPRCC_CFGR_PLLSRC%PRCC_CFGR_PLLXTPRE_PosPRCC_CFGR_PLLXTPRE_MskPRCC_CFGR_PLLXTPREvPRCC_CFGR_PLLMULL_Pos8PRCC_CFGR_PLLMULL_Msk?PRCC_CFGR_PLLMULLPRCC_CFGR_PLLMULL_0>PRCC_CFGR_PLLMULL_1=PRCC_CFGR_PLLMULL_2<PRCC_CFGR_PLLMULL_3;PRCC_CFGR_PLLXTPRE_HSE/#PRCC_CFGR_PLLXTPRE_HSE_DIV2PRCC_CFGR_PLLMULL2PRCC_CFGR_PLLMULL3_PosPRCC_CFGR_PLLMULL3_Msk PRCC_CFGR_PLLMULL3PRCC_CFGR_PLLMULL4_PosPRCC_CFGR_PLLMULL4_Msk PRCC_CFGR_PLLMULL4PRCC_CFGR_PLLMULL5_PosPRCC_CFGR_PLLMULL5_MskPRCC_CFGR_PLLMULL5PRCC_CFGR_PLLMULL6_PosPRCC_CFGR_PLLMULL6_MskPRCC_CFGR_PLLMULL6PRCC_CFGR_PLLMULL7_PosPRCC_CFGR_PLLMULL7_MskPRCC_CFGR_PLLMULL7PRCC_CFGR_PLLMULL8_PosPRCC_CFGR_PLLMULL8_MskPRCC_CFGR_PLLMULL8PRCC_CFGR_PLLMULL9_PosPRCC_CFGR_PLLMULL9_MskPRCC_CFGR_PLLMULL9PRCC_CFGR_PLLMULL10_PosPRCC_CFGR_PLLMULL10_MskPRCC_CFGR_PLLMULL10lPRCC_CFGR_PLLMULL11_PosPRCC_CFGR_PLLMULL11_MskPRCC_CFGR_PLLMULL11kPRCC_CFGR_PLLMULL12_PosPRCC_CFGR_PLLMULL12_MskPRCC_CFGR_PLLMULL12jPRCC_CFGR_PLLMULL13_PosPRCC_CFGR_PLLMULL13_MskPRCC_CFGR_PLLMULL13iPRCC_CFGR_PLLMULL14_PosPRCC_CFGR_PLLMULL14_MskPRCC_CFGR_PLLMULL14hPRCC_CFGR_PLLMULL15_PosPRCC_CFGR_PLLMULL15_MskPRCC_CFGR_PLLMULL15gPRCC_CFGR_PLLMULL16_PosPRCC_CFGR_PLLMULL16_MskPRCC_CFGR_PLLMULL16fPRCC_CFGR_USBPRE_PosPRCC_CFGR_USBPRE_MskPRCC_CFGR_USBPRE$PRCC_CFGR_MCO_PosPRCC_CFGR_MCO_MskP RCC_CFGR_MCOPRCC_CFGR_MCO_0PRCC_CFGR_MCO_1PRCC_CFGR_MCO_2PRCC_CFGR_MCO_NOCLOCKPRCC_CFGR_MCO_SYSCLKPRCC_CFGR_MCO_HSIPRCC_CFGR_MCO_HSE!PRCC_CFGR_MCO_PLLCLK_DIV2oPRCC_CFGR_MCOSEL2PRCC_CFGR_MCOSEL_0PRCC_CFGR_MCOSEL_1PRCC_CFGR_MCOSEL_2 PRCC_CFGR_MCOSEL_NOCLOCKPRCC_CFGR_MCOSEL_SYSCLKPRCC_CFGR_MCOSEL_HSIPRCC_CFGR_MCOSEL_HSE!PRCC_CFGR_MCOSEL_PLL_DIV2ePRCC_CIR_LSIRDYF_PosPRCC_CIR_LSIRDYF_MskPRCC_CIR_LSIRDYFPRCC_CIR_LSERDYF_PosPRCC_CIR_LSERDYF_MskPRCC_CIR_LSERDYF PRCC_CIR_HSIRDYF_PosPRCC_CIR_HSIRDYF_MskPRCC_CIR_HSIRDYF PRCC_CIR_HSERDYF_PosPRCC_CIR_HSERDYF_MskPRCC_CIR_HSERDYF$PRCC_CIR_PLLRDYF_PosPRCC_CIR_PLLRDYF_MskPRCC_CIR_PLLRDYFPRCC_CIR_CSSF_PoswPRCC_CIR_CSSF_Msk~P RCC_CIR_CSSFPRCC_CIR_LSIRDYIE_Pos9PRCC_CIR_LSIRDYIE_Msk@PRCC_CIR_LSIRDYIEPRCC_CIR_LSERDYIE_Pos=PRCC_CIR_LSERDYIE_MskDPRCC_CIR_LSERDYIEPRCC_CIR_HSIRDYIE_Pos=PRCC_CIR_HSIRDYIE_MskDPRCC_CIR_HSIRDYIEPRCC_CIR_HSERDYIE_PosAPRCC_CIR_HSERDYIE_MskHPRCC_CIR_HSERDYIEPRCC_CIR_PLLRDYIE_Pos9PRCC_CIR_PLLRDYIE_Msk@PRCC_CIR_PLLRDYIEPRCC_CIR_LSIRDYC_PosPRCC_CIR_LSIRDYC_MskPRCC_CIR_LSIRDYCPRCC_CIR_LSERDYC_PosPRCC_CIR_LSERDYC_MskPRCC_CIR_LSERDYC#PRCC_CIR_HSIRDYC_PosPRCC_CIR_HSIRDYC_MskPRCC_CIR_HSIRDYC#PRCC_CIR_HSERDYC_PosPRCC_CIR_HSERDYC_MskPRCC_CIR_HSERDYC'PRCC_CIR_PLLRDYC_PosPRCC_CIR_PLLRDYC_MskPRCC_CIR_PLLRDYCPRCC_CIR_CSSC_PoszPRCC_CIR_CSSC_MskP RCC_CIR_CSSC!PRCC_APB2RSTR_AFIORST_Pos !PRCC_APB2RSTR_AFIORST_MskPRCC_APB2RSTR_AFIORST!PRCC_APB2RSTR_IOPARST_Pos!PRCC_APB2RSTR_IOPARST_Msk PRCC_APB2RSTR_IOPARST!PRCC_APB2RSTR_IOPBRST_Pos!PRCC_APB2RSTR_IOPBRST_MskPRCC_APB2RSTR_IOPBRST!PRCC_APB2RSTR_IOPCRST_Pos!PRCC_APB2RSTR_IOPCRST_MskPRCC_APB2RSTR_IOPCRST!PRCC_APB2RSTR_IOPDRST_Pos!PRCC_APB2RSTR_IOPDRST_MskPRCC_APB2RSTR_IOPDRST!PRCC_APB2RSTR_ADC1RST_Pos2!PRCC_APB2RSTR_ADC1RST_Msk9PRCC_APB2RSTR_ADC1RST!PRCC_APB2RSTR_ADC2RST_Pos1!PRCC_APB2RSTR_ADC2RST_Msk8PRCC_APB2RSTR_ADC2RST!PRCC_APB2RSTR_TIM1RST_Pos!PRCC_APB2RSTR_TIM1RST_MskPRCC_APB2RSTR_TIM1RST!PRCC_APB2RSTR_SPI1RST_Pos!PRCC_APB2RSTR_SPI1RST_MskPRCC_APB2RSTR_SPI1RST#PRCC_APB2RSTR_USART1RST_Posg#PRCC_APB2RSTR_USART1RST_MsknPRCC_APB2RSTR_USART1RST!PRCC_APB2RSTR_IOPERST_Pos!PRCC_APB2RSTR_IOPERST_MskPRCC_APB2RSTR_IOPERST!PRCC_APB2RSTR_IOPFRST_Pos!PRCC_APB2RSTR_IOPFRST_MskPRCC_APB2RSTR_IOPFRST!PRCC_APB2RSTR_IOPGRST_Pos!PRCC_APB2RSTR_IOPGRST_MskPRCC_APB2RSTR_IOPGRST!PRCC_APB2RSTR_TIM8RST_Pos !PRCC_APB2RSTR_TIM8RST_MskPRCC_APB2RSTR_TIM8RST!PRCC_APB2RSTR_ADC3RST_Pos0!PRCC_APB2RSTR_ADC3RST_Msk7PRCC_APB2RSTR_ADC3RST!PRCC_APB1RSTR_TIM2RST_Pos!PRCC_APB1RSTR_TIM2RST_MskPRCC_APB1RSTR_TIM2RST!PRCC_APB1RSTR_TIM3RST_Pos!PRCC_APB1RSTR_TIM3RST_MskPRCC_APB1RSTR_TIM3RST!PRCC_APB1RSTR_WWDGRST_Pos!PRCC_APB1RSTR_WWDGRST_MskPRCC_APB1RSTR_WWDGRST#PRCC_APB1RSTR_USART2RST_Posg#PRCC_APB1RSTR_USART2RST_MsknPRCC_APB1RSTR_USART2RST!PRCC_APB1RSTR_I2C1RST_Pos=!PRCC_APB1RSTR_I2C1RST_MskDPRCC_APB1RSTR_I2C1RST!PRCC_APB1RSTR_CAN1RST_Pos)!PRCC_APB1RSTR_CAN1RST_Msk0PRCC_APB1RSTR_CAN1RST PRCC_APB1RSTR_BKPRST_PosQ PRCC_APB1RSTR_BKPRST_MskXPRCC_APB1RSTR_BKPRST PRCC_APB1RSTR_PWRRST_Pos5 PRCC_APB1RSTR_PWRRST_Msk<PRCC_APB1RSTR_PWRRST!PRCC_APB1RSTR_TIM4RST_Pos!PRCC_APB1RSTR_TIM4RST_MskPRCC_APB1RSTR_TIM4RST!PRCC_APB1RSTR_SPI2RST_Pos!PRCC_APB1RSTR_SPI2RST_MskPRCC_APB1RSTR_SPI2RST#PRCC_APB1RSTR_USART3RST_Posf#PRCC_APB1RSTR_USART3RST_MskmPRCC_APB1RSTR_USART3RST!PRCC_APB1RSTR_I2C2RST_PosPRCC_APB2ENR_USART1ENPRCC_APB2ENR_IOPEEN_PosPRCC_APB2ENR_IOPEEN_MskPRCC_APB2ENR_IOPEENgPRCC_APB2ENR_IOPFEN_PosPRCC_APB2ENR_IOPFEN_MskPRCC_APB2ENR_IOPFENfPRCC_APB2ENR_IOPGEN_PosPRCC_APB2ENR_IOPGEN_MskPRCC_APB2ENR_IOPGENePRCC_APB2ENR_TIM8EN_PosPRCC_APB2ENR_TIM8EN_MskPRCC_APB2ENR_TIM8ENrPRCC_APB2ENR_ADC3EN_PosPRCC_APB2ENR_ADC3EN_MskPRCC_APB2ENR_ADC3ENPRCC_APB1ENR_TIM2EN_PosPRCC_APB1ENR_TIM2EN_MskPRCC_APB1ENR_TIM2ENyPRCC_APB1ENR_TIM3EN_PosPRCC_APB1ENR_TIM3EN_MskPRCC_APB1ENR_TIM3ENxPRCC_APB1ENR_WWDGEN_PosPRCC_APB1ENR_WWDGEN_MskPRCC_APB1ENR_WWDGEN\!PRCC_APB1ENR_USART2EN_Pos7!PRCC_APB1ENR_USART2EN_Msk>PRCC_APB1ENR_USART2ENPRCC_APB1ENR_I2C1EN_Pos PRCC_APB1ENR_I2C1EN_MskPRCC_APB1ENR_I2C1ENPRCC_APB1ENR_CAN1EN_PosPRCC_APB1ENR_CAN1EN_MskPRCC_APB1ENR_CAN1ENPRCC_APB1ENR_BKPEN_Pos!PRCC_APB1ENR_BKPEN_Msk(PRCC_APB1ENR_BKPENPRCC_APB1ENR_PWREN_PosPRCC_APB1ENR_PWREN_Msk PRCC_APB1ENR_PWRENPRCC_APB1ENR_TIM4EN_PosPRCC_APB1ENR_TIM4EN_MskPRCC_APB1ENR_TIM4ENwPRCC_APB1ENR_SPI2EN_PosPRCC_APB1ENR_SPI2EN_MskPRCC_APB1ENR_SPI2ENw!PRCC_APB1ENR_USART3EN_Pos6!PRCC_APB1ENR_USART3EN_Msk=PRCC_APB1ENR_USART3ENPRCC_APB1ENR_I2C2EN_Pos PRCC_APB1ENR_I2C2EN_MskPRCC_APB1ENR_I2C2ENPRCC_APB1ENR_USBEN_PosPRCC_APB1ENR_USBEN_MskPRCC_APB1ENR_USBENPRCC_APB1ENR_TIM5EN_PosPRCC_APB1ENR_TIM5EN_MskPRCC_APB1ENR_TIM5ENvPRCC_APB1ENR_TIM6EN_PosPRCC_APB1ENR_TIM6EN_MskPRCC_APB1ENR_TIM6ENuPRCC_APB1ENR_TIM7EN_PosPRCC_APB1ENR_TIM7EN_MskPRCC_APB1ENR_TIM7ENtPRCC_APB1ENR_SPI3EN_PosPRCC_APB1ENR_SPI3EN_MskPRCC_APB1ENR_SPI3ENv PRCC_APB1ENR_UART4EN_Pos PRCC_APB1ENR_UART4EN_MskPRCC_APB1ENR_UART4EN# PRCC_APB1ENR_UART5EN_Pos PRCC_APB1ENR_UART5EN_MskPRCC_APB1ENR_UART5EN"PRCC_APB1ENR_DACEN_Pos6PRCC_APB1ENR_DACEN_Msk=PRCC_APB1ENR_DACENPRCC_BDCR_LSEON_PosPRCC_BDCR_LSEON_MskPRCC_BDCR_LSEON}PRCC_BDCR_LSERDY_PosPRCC_BDCR_LSERDY_MskPRCC_BDCR_LSERDY)PRCC_BDCR_LSEBYP_PosPRCC_BDCR_LSEBYP_MskPRCC_BDCR_LSEBYP-PRCC_BDCR_RTCSEL_PosPRCC_BDCR_RTCSEL_MskPRCC_BDCR_RTCSEL/PRCC_BDCR_RTCSEL_0PRCC_BDCR_RTCSEL_1 PRCC_BDCR_RTCSEL_NOCLOCKPRCC_BDCR_RTCSEL_LSEPRCC_BDCR_RTCSEL_LSIPRCC_BDCR_RTCSEL_HSEPRCC_BDCR_RTCEN_PosPRCC_BDCR_RTCEN_MskPRCC_BDCR_RTCENPRCC_BDCR_BDRST_PosPRCC_BDCR_BDRST_MskPRCC_BDCR_BDRSTPRCC_CSR_LSION_PosPRCC_CSR_LSION_MskPRCC_CSR_LSIONPRCC_CSR_LSIRDY_PosPRCC_CSR_LSIRDY_MskPRCC_CSR_LSIRDYZPRCC_CSR_RMVF_PosaPRCC_CSR_RMVF_MskhP RCC_CSR_RMVFPRCC_CSR_PINRSTF_PospPRCC_CSR_PINRSTF_MskwPRCC_CSR_PINRSTF PRCC_CSR_PORRSTF_PosfPRCC_CSR_PORRSTF_MskmPRCC_CSR_PORRSTFPRCC_CSR_SFTRSTF_PosjPRCC_CSR_SFTRSTF_MskqPRCC_CSR_SFTRSTFPRCC_CSR_IWDGRSTF_Pos*PRCC_CSR_IWDGRSTF_Msk1PRCC_CSR_IWDGRSTFPRCC_CSR_WWDGRSTF_PosPRCC_CSR_WWDGRSTF_Msk#PRCC_CSR_WWDGRSTFPRCC_CSR_LPWRRSTF_PosPRCC_CSR_LPWRRSTF_MskPRCC_CSR_LPWRRSTFPGPIO_CRL_MODE_Pos%PGPIO_CRL_MODE_Msk,PGPIO_CRL_MODEPGPIO_CRL_MODE0_PosPGPIO_CRL_MODE0_MskPGPIO_CRL_MODE0PGPIO_CRL_MODE0_0PGPIO_CRL_MODE0_1PGPIO_CRL_MODE1_PosPGPIO_CRL_MODE1_MskPGPIO_CRL_MODE1PGPIO_CRL_MODE1_0PGPIO_CRL_MODE1_1PGPIO_CRL_MODE2_PosPGPIO_CRL_MODE2_MskPGPIO_CRL_MODE2PGPIO_CRL_MODE2_0PGPIO_CRL_MODE2_1PGPIO_CRL_MODE3_PosPGPIO_CRL_MODE3_MskPGPIO_CRL_MODE3PGPIO_CRL_MODE3_0PGPIO_CRL_MODE3_1PGPIO_CRL_MODE4_PosPGPIO_CRL_MODE4_MskPGPIO_CRL_MODE4PGPIO_CRL_MODE4_0PGPIO_CRL_MODE4_1PGPIO_CRL_MODE5_PosPGPIO_CRL_MODE5_MskPGPIO_CRL_MODE5PGPIO_CRL_MODE5_0PGPIO_CRL_MODE5_1PGPIO_CRL_MODE6_PosPGPIO_CRL_MODE6_MskPGPIO_CRL_MODE6PGPIO_CRL_MODE6_0PGPIO_CRL_MODE6_1PGPIO_CRL_MODE7_PosPGPIO_CRL_MODE7_MskPGPIO_CRL_MODE7PGPIO_CRL_MODE7_0PGPIO_CRL_MODE7_1PGPIO_CRL_CNF_PosuPGPIO_CRL_CNF_Msk|P GPIO_CRL_CNFPGPIO_CRL_CNF0_PosCPGPIO_CRL_CNF0_MskJPGPIO_CRL_CNF0PGPIO_CRL_CNF0_0IPGPIO_CRL_CNF0_1HPGPIO_CRL_CNF1_PosBPGPIO_CRL_CNF1_MskIPGPIO_CRL_CNF1PGPIO_CRL_CNF1_0HPGPIO_CRL_CNF1_1GPGPIO_CRL_CNF2_PosAPGPIO_CRL_CNF2_MskHPGPIO_CRL_CNF2PGPIO_CRL_CNF2_0GPGPIO_CRL_CNF2_1FPGPIO_CRL_CNF3_Pos@PGPIO_CRL_CNF3_MskGPGPIO_CRL_CNF3PGPIO_CRL_CNF3_0FPGPIO_CRL_CNF3_1EPGPIO_CRL_CNF4_Pos?PGPIO_CRL_CNF4_MskFPGPIO_CRL_CNF4PGPIO_CRL_CNF4_0EPGPIO_CRL_CNF4_1DPGPIO_CRL_CNF5_Pos>PGPIO_CRL_CNF5_MskEPGPIO_CRL_CNF5PGPIO_CRL_CNF5_0DPGPIO_CRL_CNF5_1CPGPIO_CRL_CNF6_Pos=PGPIO_CRL_CNF6_MskDPGPIO_CRL_CNF6PGPIO_CRL_CNF6_0CPGPIO_CRL_CNF6_1BPGPIO_CRL_CNF7_Pos<PGPIO_CRL_CNF7_MskCPGPIO_CRL_CNF7PGPIO_CRL_CNF7_0BPGPIO_CRL_CNF7_1APGPIO_CRH_MODE_Pos)PGPIO_CRH_MODE_Msk0PGPIO_CRH_MODEPGPIO_CRH_MODE8_PosPGPIO_CRH_MODE8_MskPGPIO_CRH_MODE8PGPIO_CRH_MODE8_0PGPIO_CRH_MODE8_1PGPIO_CRH_MODE9_PosPGPIO_CRH_MODE9_MskPGPIO_CRH_MODE9PGPIO_CRH_MODE9_0PGPIO_CRH_MODE9_1PGPIO_CRH_MODE10_PosPGPIO_CRH_MODE10_MskPGPIO_CRH_MODE10]PGPIO_CRH_MODE10_0PGPIO_CRH_MODE10_1PGPIO_CRH_MODE11_PosPGPIO_CRH_MODE11_MskPGPIO_CRH_MODE11\PGPIO_CRH_MODE11_0PGPIO_CRH_MODE11_1PGPIO_CRH_MODE12_PosPGPIO_CRH_MODE12_MskPGPIO_CRH_MODE12[PGPIO_CRH_MODE12_0PGPIO_CRH_MODE12_1PGPIO_CRH_MODE13_PosPGPIO_CRH_MODE13_MskPGPIO_CRH_MODE13ZPGPIO_CRH_MODE13_0PGPIO_CRH_MODE13_1PGPIO_CRH_MODE14_PosPGPIO_CRH_MODE14_MskPGPIO_CRH_MODE14YPGPIO_CRH_MODE14_0PGPIO_CRH_MODE14_1PGPIO_CRH_MODE15_PosPGPIO_CRH_MODE15_MskPGPIO_CRH_MODE15XPGPIO_CRH_MODE15_0PGPIO_CRH_MODE15_1PGPIO_CRH_CNF_PosyPGPIO_CRH_CNF_MskP GPIO_CRH_CNFPGPIO_CRH_CNF8_Pos?PGPIO_CRH_CNF8_MskFPGPIO_CRH_CNF8PGPIO_CRH_CNF8_0EPGPIO_CRH_CNF8_1DPGPIO_CRH_CNF9_Pos>PGPIO_CRH_CNF9_MskEPGPIO_CRH_CNF9PGPIO_CRH_CNF9_0DPGPIO_CRH_CNF9_1CPGPIO_CRH_CNF10_PosPGPIO_CRH_CNF10_MskPGPIO_CRH_CNF10PGPIO_CRH_CNF10_0PGPIO_CRH_CNF10_1PGPIO_CRH_CNF11_PosPGPIO_CRH_CNF11_MskPGPIO_CRH_CNF11PGPIO_CRH_CNF11_0PGPIO_CRH_CNF11_1PGPIO_CRH_CNF12_PosPGPIO_CRH_CNF12_MskPGPIO_CRH_CNF12PGPIO_CRH_CNF12_0PGPIO_CRH_CNF12_1PGPIO_CRH_CNF13_PosPGPIO_CRH_CNF13_MskPGPIO_CRH_CNF13PGPIO_CRH_CNF13_0PGPIO_CRH_CNF13_1PGPIO_CRH_CNF14_PosPGPIO_CRH_CNF14_MskPGPIO_CRH_CNF14PGPIO_CRH_CNF14_0PGPIO_CRH_CNF14_1PGPIO_CRH_CNF15_PosPGPIO_CRH_CNF15_MskPGPIO_CRH_CNF15PGPIO_CRH_CNF15_0PGPIO_CRH_CNF15_1PGPIO_IDR_IDR0_Pos=PGPIO_IDR_IDR0_MskDPGPIO_IDR_IDR0PGPIO_IDR_IDR1_Pos<PGPIO_IDR_IDR1_MskCPGPIO_IDR_IDR1PGPIO_IDR_IDR2_Pos;PGPIO_IDR_IDR2_MskBPGPIO_IDR_IDR2PGPIO_IDR_IDR3_Pos:PGPIO_IDR_IDR3_MskAPGPIO_IDR_IDR3PGPIO_IDR_IDR4_Pos9PGPIO_IDR_IDR4_Msk@PGPIO_IDR_IDR4PGPIO_IDR_IDR5_Pos8PGPIO_IDR_IDR5_Msk?PGPIO_IDR_IDR5PGPIO_IDR_IDR6_Pos7PGPIO_IDR_IDR6_Msk>PGPIO_IDR_IDR6PGPIO_IDR_IDR7_Pos6PGPIO_IDR_IDR7_Msk=PGPIO_IDR_IDR7PGPIO_IDR_IDR8_Pos5PGPIO_IDR_IDR8_Msk<PGPIO_IDR_IDR8PGPIO_IDR_IDR9_Pos4PGPIO_IDR_IDR9_Msk;PGPIO_IDR_IDR9PGPIO_IDR_IDR10_Pos PGPIO_IDR_IDR10_MskPGPIO_IDR_IDR10PGPIO_IDR_IDR11_Pos PGPIO_IDR_IDR11_MskPGPIO_IDR_IDR11PGPIO_IDR_IDR12_PosPGPIO_IDR_IDR12_MskPGPIO_IDR_IDR12PGPIO_IDR_IDR13_PosPGPIO_IDR_IDR13_MskPGPIO_IDR_IDR13PGPIO_IDR_IDR14_PosPGPIO_IDR_IDR14_Msk PGPIO_IDR_IDR14PGPIO_IDR_IDR15_PosPGPIO_IDR_IDR15_Msk PGPIO_IDR_IDR15PGPIO_ODR_ODR0_Pos1PGPIO_ODR_ODR0_Msk8PGPIO_ODR_ODR0PGPIO_ODR_ODR1_Pos0PGPIO_ODR_ODR1_Msk7PGPIO_ODR_ODR1PGPIO_ODR_ODR2_Pos/PGPIO_ODR_ODR2_Msk6PGPIO_ODR_ODR2PGPIO_ODR_ODR3_Pos.PGPIO_ODR_ODR3_Msk5PGPIO_ODR_ODR3PGPIO_ODR_ODR4_Pos-PGPIO_ODR_ODR4_Msk4PGPIO_ODR_ODR4PGPIO_ODR_ODR5_Pos,PGPIO_ODR_ODR5_Msk3PGPIO_ODR_ODR5PGPIO_ODR_ODR6_Pos+PGPIO_ODR_ODR6_Msk2PGPIO_ODR_ODR6PGPIO_ODR_ODR7_Pos*PGPIO_ODR_ODR7_Msk1PGPIO_ODR_ODR7PGPIO_ODR_ODR8_Pos)PGPIO_ODR_ODR8_Msk0PGPIO_ODR_ODR8PGPIO_ODR_ODR9_Pos(PGPIO_ODR_ODR9_Msk/PGPIO_ODR_ODR9PGPIO_ODR_ODR10_PosPGPIO_ODR_ODR10_MskPGPIO_ODR_ODR10PGPIO_ODR_ODR11_PosPGPIO_ODR_ODR11_MskPGPIO_ODR_ODR11PGPIO_ODR_ODR12_PosPGPIO_ODR_ODR12_MskPGPIO_ODR_ODR12PGPIO_ODR_ODR13_PosPGPIO_ODR_ODR13_MskPGPIO_ODR_ODR13PGPIO_ODR_ODR14_PosPGPIO_ODR_ODR14_MskPGPIO_ODR_ODR14PGPIO_ODR_ODR15_PosPGPIO_ODR_ODR15_MskPGPIO_ODR_ODR15PGPIO_BSRR_BS0_Pos-PGPIO_BSRR_BS0_Msk4PGPIO_BSRR_BS0PGPIO_BSRR_BS1_Pos,PGPIO_BSRR_BS1_Msk3PGPIO_BSRR_BS1PGPIO_BSRR_BS2_Pos+PGPIO_BSRR_BS2_Msk2PGPIO_BSRR_BS2PGPIO_BSRR_BS3_Pos*PGPIO_BSRR_BS3_Msk1PGPIO_BSRR_BS3PGPIO_BSRR_BS4_Pos)PGPIO_BSRR_BS4_Msk0PGPIO_BSRR_BS4PGPIO_BSRR_BS5_Pos(PGPIO_BSRR_BS5_Msk/PGPIO_BSRR_BS5PGPIO_BSRR_BS6_Pos'PGPIO_BSRR_BS6_Msk.PGPIO_BSRR_BS6PGPIO_BSRR_BS7_Pos&PGPIO_BSRR_BS7_Msk-PGPIO_BSRR_BS7PGPIO_BSRR_BS8_Pos%PGPIO_BSRR_BS8_Msk,PGPIO_BSRR_BS8PGPIO_BSRR_BS9_Pos$PGPIO_BSRR_BS9_Msk+PGPIO_BSRR_BS9PGPIO_BSRR_BS10_PosPGPIO_BSRR_BS10_MskPGPIO_BSRR_BS10PGPIO_BSRR_BS11_PosPGPIO_BSRR_BS11_MskPGPIO_BSRR_BS11PGPIO_BSRR_BS12_PosPGPIO_BSRR_BS12_MskPGPIO_BSRR_BS12PGPIO_BSRR_BS13_PosPGPIO_BSRR_BS13_MskPGPIO_BSRR_BS13PGPIO_BSRR_BS14_PosPGPIO_BSRR_BS14_MskPGPIO_BSRR_BS14PGPIO_BSRR_BS15_PosPGPIO_BSRR_BS15_MskPGPIO_BSRR_BS15PGPIO_BSRR_BR0_Pos.PGPIO_BSRR_BR0_Msk5PGPIO_BSRR_BR0PGPIO_BSRR_BR1_Pos-PGPIO_BSRR_BR1_Msk4PGPIO_BSRR_BR1PGPIO_BSRR_BR2_Pos,PGPIO_BSRR_BR2_Msk3PGPIO_BSRR_BR2PGPIO_BSRR_BR3_Pos+PGPIO_BSRR_BR3_Msk2PGPIO_BSRR_BR3PGPIO_BSRR_BR4_Pos*PGPIO_BSRR_BR4_Msk1PGPIO_BSRR_BR4PGPIO_BSRR_BR5_Pos)PGPIO_BSRR_BR5_Msk0PGPIO_BSRR_BR5PGPIO_BSRR_BR6_Pos(PGPIO_BSRR_BR6_Msk/PGPIO_BSRR_BR6PGPIO_BSRR_BR7_Pos'PGPIO_BSRR_BR7_Msk.PGPIO_BSRR_BR7PGPIO_BSRR_BR8_Pos&PGPIO_BSRR_BR8_Msk-PGPIO_BSRR_BR8PGPIO_BSRR_BR9_Pos%PGPIO_BSRR_BR9_Msk,PGPIO_BSRR_BR9PGPIO_BSRR_BR10_PosPGPIO_BSRR_BR10_MskPGPIO_BSRR_BR10PGPIO_BSRR_BR11_PosPGPIO_BSRR_BR11_MskPGPIO_BSRR_BR11PGPIO_BSRR_BR12_PosPGPIO_BSRR_BR12_MskPGPIO_BSRR_BR12PGPIO_BSRR_BR13_PosPGPIO_BSRR_BR13_MskPGPIO_BSRR_BR13PGPIO_BSRR_BR14_PosPGPIO_BSRR_BR14_MskPGPIO_BSRR_BR14PGPIO_BSRR_BR15_PosPGPIO_BSRR_BR15_MskPGPIO_BSRR_BR15PGPIO_BRR_BR0_PosPGPIO_BRR_BR0_MskP GPIO_BRR_BR0PGPIO_BRR_BR1_PosPGPIO_BRR_BR1_MskP GPIO_BRR_BR1PGPIO_BRR_BR2_PosPGPIO_BRR_BR2_MskP GPIO_BRR_BR2PGPIO_BRR_BR3_PosPGPIO_BRR_BR3_MskP GPIO_BRR_BR3PGPIO_BRR_BR4_PosPGPIO_BRR_BR4_MskP GPIO_BRR_BR4PGPIO_BRR_BR5_Pos~PGPIO_BRR_BR5_MskP GPIO_BRR_BR5PGPIO_BRR_BR6_Pos}PGPIO_BRR_BR6_MskP GPIO_BRR_BR6PGPIO_BRR_BR7_Pos|PGPIO_BRR_BR7_MskP GPIO_BRR_BR7PGPIO_BRR_BR8_Pos{PGPIO_BRR_BR8_MskP GPIO_BRR_BR8PGPIO_BRR_BR9_PoszPGPIO_BRR_BR9_MskP GPIO_BRR_BR9PGPIO_BRR_BR10_PosPPGPIO_BRR_BR10_MskWPGPIO_BRR_BR10PGPIO_BRR_BR11_PosOPGPIO_BRR_BR11_MskVPGPIO_BRR_BR11PGPIO_BRR_BR12_PosNPGPIO_BRR_BR12_MskUPGPIO_BRR_BR12PGPIO_BRR_BR13_PosMPGPIO_BRR_BR13_MskTPGPIO_BRR_BR13PGPIO_BRR_BR14_PosLPGPIO_BRR_BR14_MskSPGPIO_BRR_BR14PGPIO_BRR_BR15_PosKPGPIO_BRR_BR15_MskRPGPIO_BRR_BR15PGPIO_LCKR_LCK0_PosPGPIO_LCKR_LCK0_MskPGPIO_LCKR_LCK0PGPIO_LCKR_LCK1_PosPGPIO_LCKR_LCK1_MskPGPIO_LCKR_LCK1PGPIO_LCKR_LCK2_PosPGPIO_LCKR_LCK2_MskPGPIO_LCKR_LCK2PGPIO_LCKR_LCK3_PosPGPIO_LCKR_LCK3_MskPGPIO_LCKR_LCK3PGPIO_LCKR_LCK4_PosPGPIO_LCKR_LCK4_MskPGPIO_LCKR_LCK4PGPIO_LCKR_LCK5_PosPGPIO_LCKR_LCK5_MskPGPIO_LCKR_LCK5PGPIO_LCKR_LCK6_PosPGPIO_LCKR_LCK6_MskPGPIO_LCKR_LCK6PGPIO_LCKR_LCK7_PosPGPIO_LCKR_LCK7_MskPGPIO_LCKR_LCK7PGPIO_LCKR_LCK8_PosPGPIO_LCKR_LCK8_MskPGPIO_LCKR_LCK8PGPIO_LCKR_LCK9_PosPGPIO_LCKR_LCK9_MskPGPIO_LCKR_LCK9PGPIO_LCKR_LCK10_PosPGPIO_LCKR_LCK10_MskPGPIO_LCKR_LCK10YPGPIO_LCKR_LCK11_PosPGPIO_LCKR_LCK11_MskPGPIO_LCKR_LCK11XPGPIO_LCKR_LCK12_PosPGPIO_LCKR_LCK12_MskPGPIO_LCKR_LCK12WPGPIO_LCKR_LCK13_PosPGPIO_LCKR_LCK13_MskPGPIO_LCKR_LCK13VPGPIO_LCKR_LCK14_PosPGPIO_LCKR_LCK14_MskPGPIO_LCKR_LCK14UPGPIO_LCKR_LCK15_PosPGPIO_LCKR_LCK15_MskPGPIO_LCKR_LCK15TPGPIO_LCKR_LCKK_PosPGPIO_LCKR_LCKK_MskPGPIO_LCKR_LCKKqPAFIO_EVCR_PIN_Pos$PAFIO_EVCR_PIN_Msk+PAFIO_EVCR_PINPAFIO_EVCR_PIN_0*PAFIO_EVCR_PIN_1)PAFIO_EVCR_PIN_2(PAFIO_EVCR_PIN_3'PAFIO_EVCR_PIN_PX0~PAFIO_EVCR_PIN_PX1_PosPAFIO_EVCR_PIN_PX1_MskPAFIO_EVCR_PIN_PX1}PAFIO_EVCR_PIN_PX2_PosPAFIO_EVCR_PIN_PX2_MskPAFIO_EVCR_PIN_PX2|PAFIO_EVCR_PIN_PX3_PosPAFIO_EVCR_PIN_PX3_MskPAFIO_EVCR_PIN_PX3{PAFIO_EVCR_PIN_PX4_PosPAFIO_EVCR_PIN_PX4_MskPAFIO_EVCR_PIN_PX4zPAFIO_EVCR_PIN_PX5_PosPAFIO_EVCR_PIN_PX5_MskPAFIO_EVCR_PIN_PX5yPAFIO_EVCR_PIN_PX6_PosPAFIO_EVCR_PIN_PX6_MskPAFIO_EVCR_PIN_PX6xPAFIO_EVCR_PIN_PX7_PosPAFIO_EVCR_PIN_PX7_MskPAFIO_EVCR_PIN_PX7wPAFIO_EVCR_PIN_PX8_PosPAFIO_EVCR_PIN_PX8_MskPAFIO_EVCR_PIN_PX8vPAFIO_EVCR_PIN_PX9_PosPAFIO_EVCR_PIN_PX9_MskPAFIO_EVCR_PIN_PX9uPAFIO_EVCR_PIN_PX10_PosPAFIO_EVCR_PIN_PX10_MskPAFIO_EVCR_PIN_PX10KPAFIO_EVCR_PIN_PX11_PosPAFIO_EVCR_PIN_PX11_MskPAFIO_EVCR_PIN_PX11JPAFIO_EVCR_PIN_PX12_PosPAFIO_EVCR_PIN_PX12_MskPAFIO_EVCR_PIN_PX12IPAFIO_EVCR_PIN_PX13_PosPAFIO_EVCR_PIN_PX13_MskPAFIO_EVCR_PIN_PX13HPAFIO_EVCR_PIN_PX14_PosPAFIO_EVCR_PIN_PX14_MskPAFIO_EVCR_PIN_PX14GPAFIO_EVCR_PIN_PX15_PosPAFIO_EVCR_PIN_PX15_MskPAFIO_EVCR_PIN_PX15FPAFIO_EVCR_PORT_PosPAFIO_EVCR_PORT_MskPAFIO_EVCR_PORT]PAFIO_EVCR_PORT_0PAFIO_EVCR_PORT_1PAFIO_EVCR_PORT_2PAFIO_EVCR_PORT_PAgPAFIO_EVCR_PORT_PB_PosPAFIO_EVCR_PORT_PB_MskPAFIO_EVCR_PORT_PBfPAFIO_EVCR_PORT_PC_PosPAFIO_EVCR_PORT_PC_MskPAFIO_EVCR_PORT_PCePAFIO_EVCR_PORT_PD_PosPAFIO_EVCR_PORT_PD_MskPAFIO_EVCR_PORT_PDdPAFIO_EVCR_PORT_PE_PosPAFIO_EVCR_PORT_PE_MskPAFIO_EVCR_PORT_PEcPAFIO_EVCR_EVOE_PosPAFIO_EVCR_EVOE_MskPAFIO_EVCR_EVOEs!PAFIO_MAPR_SPI1_REMAP_Pos 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PAFIO_EXTICR4_EXTI12_Pos PAFIO_EXTICR4_EXTI12_MskPAFIO_EXTICR4_EXTI12( PAFIO_EXTICR4_EXTI13_Pos PAFIO_EXTICR4_EXTI13_MskPAFIO_EXTICR4_EXTI13' PAFIO_EXTICR4_EXTI14_Pos PAFIO_EXTICR4_EXTI14_MskPAFIO_EXTICR4_EXTI14& PAFIO_EXTICR4_EXTI15_Pos PAFIO_EXTICR4_EXTI15_MskPAFIO_EXTICR4_EXTI15%PAFIO_EXTICR4_EXTI12_PA2#PAFIO_EXTICR4_EXTI12_PB_Pos#PAFIO_EXTICR4_EXTI12_PB_MskPAFIO_EXTICR4_EXTI12_PB1#PAFIO_EXTICR4_EXTI12_PC_Pos#PAFIO_EXTICR4_EXTI12_PC_MskPAFIO_EXTICR4_EXTI12_PC0#PAFIO_EXTICR4_EXTI12_PD_Pos#PAFIO_EXTICR4_EXTI12_PD_MskPAFIO_EXTICR4_EXTI12_PD/#PAFIO_EXTICR4_EXTI12_PE_Pos#PAFIO_EXTICR4_EXTI12_PE_MskPAFIO_EXTICR4_EXTI12_PE.#PAFIO_EXTICR4_EXTI12_PF_Pos#PAFIO_EXTICR4_EXTI12_PF_MskPAFIO_EXTICR4_EXTI12_PF-#PAFIO_EXTICR4_EXTI12_PG_Pos#PAFIO_EXTICR4_EXTI12_PG_MskPAFIO_EXTICR4_EXTI12_PG,PAFIO_EXTICR4_EXTI13_PA1#PAFIO_EXTICR4_EXTI13_PB_Pos#PAFIO_EXTICR4_EXTI13_PB_MskPAFIO_EXTICR4_EXTI13_PB0#PAFIO_EXTICR4_EXTI13_PC_Pos#PAFIO_EXTICR4_EXTI13_PC_MskPAFIO_EXTICR4_EXTI13_PC/#PAFIO_EXTICR4_EXTI13_PD_Pos#PAFIO_EXTICR4_EXTI13_PD_MskPAFIO_EXTICR4_EXTI13_PD.#PAFIO_EXTICR4_EXTI13_PE_Pos#PAFIO_EXTICR4_EXTI13_PE_MskPAFIO_EXTICR4_EXTI13_PE-#PAFIO_EXTICR4_EXTI13_PF_Pos#PAFIO_EXTICR4_EXTI13_PF_MskPAFIO_EXTICR4_EXTI13_PF,#PAFIO_EXTICR4_EXTI13_PG_Pos#PAFIO_EXTICR4_EXTI13_PG_MskPAFIO_EXTICR4_EXTI13_PG+PAFIO_EXTICR4_EXTI14_PA0#PAFIO_EXTICR4_EXTI14_PB_Pos#PAFIO_EXTICR4_EXTI14_PB_MskPAFIO_EXTICR4_EXTI14_PB/#PAFIO_EXTICR4_EXTI14_PC_Pos#PAFIO_EXTICR4_EXTI14_PC_MskPAFIO_EXTICR4_EXTI14_PC.#PAFIO_EXTICR4_EXTI14_PD_Pos#PAFIO_EXTICR4_EXTI14_PD_MskPAFIO_EXTICR4_EXTI14_PD-#PAFIO_EXTICR4_EXTI14_PE_Pos#PAFIO_EXTICR4_EXTI14_PE_MskPAFIO_EXTICR4_EXTI14_PE,#PAFIO_EXTICR4_EXTI14_PF_Pos#PAFIO_EXTICR4_EXTI14_PF_MskPAFIO_EXTICR4_EXTI14_PF+#PAFIO_EXTICR4_EXTI14_PG_Pos#PAFIO_EXTICR4_EXTI14_PG_MskPAFIO_EXTICR4_EXTI14_PG*PAFIO_EXTICR4_EXTI15_PA/#PAFIO_EXTICR4_EXTI15_PB_Pos#PAFIO_EXTICR4_EXTI15_PB_MskPAFIO_EXTICR4_EXTI15_PB.#PAFIO_EXTICR4_EXTI15_PC_Pos#PAFIO_EXTICR4_EXTI15_PC_MskPAFIO_EXTICR4_EXTI15_PC-#PAFIO_EXTICR4_EXTI15_PD_Pos#PAFIO_EXTICR4_EXTI15_PD_MskPAFIO_EXTICR4_EXTI15_PD,#PAFIO_EXTICR4_EXTI15_PE_Pos#PAFIO_EXTICR4_EXTI15_PE_MskPAFIO_EXTICR4_EXTI15_PE+#PAFIO_EXTICR4_EXTI15_PF_Pos#PAFIO_EXTICR4_EXTI15_PF_MskPAFIO_EXTICR4_EXTI15_PF*#PAFIO_EXTICR4_EXTI15_PG_Pos#PAFIO_EXTICR4_EXTI15_PG_MskPAFIO_EXTICR4_EXTI15_PG)'PAFIO_MAPR2_FSMC_NADV_REMAP_Pos:'PAFIO_MAPR2_FSMC_NADV_REMAP_MskA#PAFIO_MAPR2_FSMC_NADV_REMAPPEXTI_IMR_MR0_PoskPEXTI_IMR_MR0_MskrP EXTI_IMR_MR0PEXTI_IMR_MR1_PosjPEXTI_IMR_MR1_MskqP EXTI_IMR_MR1PEXTI_IMR_MR2_PosiPEXTI_IMR_MR2_MskpP EXTI_IMR_MR2PEXTI_IMR_MR3_PoshPEXTI_IMR_MR3_MskoP EXTI_IMR_MR3PEXTI_IMR_MR4_PosgPEXTI_IMR_MR4_MsknP EXTI_IMR_MR4PEXTI_IMR_MR5_PosfPEXTI_IMR_MR5_MskmP EXTI_IMR_MR5PEXTI_IMR_MR6_PosePEXTI_IMR_MR6_MsklP EXTI_IMR_MR6PEXTI_IMR_MR7_PosdPEXTI_IMR_MR7_MskkP EXTI_IMR_MR7PEXTI_IMR_MR8_PoscPEXTI_IMR_MR8_MskjP EXTI_IMR_MR8PEXTI_IMR_MR9_PosbPEXTI_IMR_MR9_MskiP EXTI_IMR_MR9PEXTI_IMR_MR10_Pos8PEXTI_IMR_MR10_Msk?PEXTI_IMR_MR10PEXTI_IMR_MR11_Pos7PEXTI_IMR_MR11_Msk>PEXTI_IMR_MR11PEXTI_IMR_MR12_Pos6PEXTI_IMR_MR12_Msk=PEXTI_IMR_MR12PEXTI_IMR_MR13_Pos5PEXTI_IMR_MR13_Msk<PEXTI_IMR_MR13PEXTI_IMR_MR14_Pos4PEXTI_IMR_MR14_Msk;PEXTI_IMR_MR14PEXTI_IMR_MR15_Pos3PEXTI_IMR_MR15_Msk:PEXTI_IMR_MR15PEXTI_IMR_MR16_Pos2PEXTI_IMR_MR16_Msk9PEXTI_IMR_MR16PEXTI_IMR_MR17_Pos1PEXTI_IMR_MR17_Msk8PEXTI_IMR_MR17PEXTI_IMR_MR18_Pos0PEXTI_IMR_MR18_Msk7PEXTI_IMR_MR18P EXTI_IMR_IM0 P EXTI_IMR_IM1 P EXTI_IMR_IM2 P EXTI_IMR_IM3 P EXTI_IMR_IM4 P EXTI_IMR_IM5P EXTI_IMR_IM6P EXTI_IMR_IM7P EXTI_IMR_IM8P EXTI_IMR_IM9PEXTI_IMR_IM10PEXTI_IMR_IM11PEXTI_IMR_IM12PEXTI_IMR_IM13PEXTI_IMR_IM14PEXTI_IMR_IM15PEXTI_IMR_IM16PEXTI_IMR_IM17PEXTI_IMR_IM18P EXTI_IMR_IM?PEXTI_EMR_MR0_PosoPEXTI_EMR_MR0_MskvP EXTI_EMR_MR0PEXTI_EMR_MR1_PosnPEXTI_EMR_MR1_MskuP EXTI_EMR_MR1PEXTI_EMR_MR2_PosmPEXTI_EMR_MR2_MsktP EXTI_EMR_MR2PEXTI_EMR_MR3_PoslPEXTI_EMR_MR3_MsksP EXTI_EMR_MR3PEXTI_EMR_MR4_PoskPEXTI_EMR_MR4_MskrP EXTI_EMR_MR4PEXTI_EMR_MR5_PosjPEXTI_EMR_MR5_MskqP EXTI_EMR_MR5PEXTI_EMR_MR6_PosiPEXTI_EMR_MR6_MskpP EXTI_EMR_MR6PEXTI_EMR_MR7_PoshPEXTI_EMR_MR7_MskoP EXTI_EMR_MR7PEXTI_EMR_MR8_PosgPEXTI_EMR_MR8_MsknP EXTI_EMR_MR8PEXTI_EMR_MR9_PosfPEXTI_EMR_MR9_MskmP EXTI_EMR_MR9PEXTI_EMR_MR10_Pos<PEXTI_EMR_MR10_MskCPEXTI_EMR_MR10PEXTI_EMR_MR11_Pos;PEXTI_EMR_MR11_MskBPEXTI_EMR_MR11PEXTI_EMR_MR12_Pos:PEXTI_EMR_MR12_MskAPEXTI_EMR_MR12PEXTI_EMR_MR13_Pos9PEXTI_EMR_MR13_Msk@PEXTI_EMR_MR13PEXTI_EMR_MR14_Pos8PEXTI_EMR_MR14_Msk?PEXTI_EMR_MR14PEXTI_EMR_MR15_Pos7PEXTI_EMR_MR15_Msk>PEXTI_EMR_MR15PEXTI_EMR_MR16_Pos6PEXTI_EMR_MR16_Msk=PEXTI_EMR_MR16PEXTI_EMR_MR17_Pos5PEXTI_EMR_MR17_Msk<PEXTI_EMR_MR17PEXTI_EMR_MR18_Pos4PEXTI_EMR_MR18_Msk;PEXTI_EMR_MR18P EXTI_EMR_EM0P EXTI_EMR_EM1P EXTI_EMR_EM2P EXTI_EMR_EM3P EXTI_EMR_EM4P EXTI_EMR_EM5P EXTI_EMR_EM6P EXTI_EMR_EM7P EXTI_EMR_EM8 P EXTI_EMR_EM9 PEXTI_EMR_EM10PEXTI_EMR_EM11PEXTI_EMR_EM12PEXTI_EMR_EM13PEXTI_EMR_EM14PEXTI_EMR_EM15PEXTI_EMR_EM16PEXTI_EMR_EM17PEXTI_EMR_EM18PEXTI_RTSR_TR0_PosPEXTI_RTSR_TR0_MskPEXTI_RTSR_TR0PEXTI_RTSR_TR1_PosPEXTI_RTSR_TR1_MskPEXTI_RTSR_TR1PEXTI_RTSR_TR2_PosPEXTI_RTSR_TR2_MskPEXTI_RTSR_TR2PEXTI_RTSR_TR3_PosPEXTI_RTSR_TR3_MskPEXTI_RTSR_TR3PEXTI_RTSR_TR4_PosPEXTI_RTSR_TR4_MskPEXTI_RTSR_TR4PEXTI_RTSR_TR5_PosPEXTI_RTSR_TR5_MskPEXTI_RTSR_TR5PEXTI_RTSR_TR6_PosPEXTI_RTSR_TR6_MskPEXTI_RTSR_TR6PEXTI_RTSR_TR7_PosPEXTI_RTSR_TR7_MskPEXTI_RTSR_TR7PEXTI_RTSR_TR8_PosPEXTI_RTSR_TR8_MskPEXTI_RTSR_TR8PEXTI_RTSR_TR9_PosPEXTI_RTSR_TR9_MskPEXTI_RTSR_TR9PEXTI_RTSR_TR10_PosPEXTI_RTSR_TR10_MskPEXTI_RTSR_TR10ePEXTI_RTSR_TR11_PosPEXTI_RTSR_TR11_MskPEXTI_RTSR_TR11dPEXTI_RTSR_TR12_PosPEXTI_RTSR_TR12_MskPEXTI_RTSR_TR12cPEXTI_RTSR_TR13_PosPEXTI_RTSR_TR13_MskPEXTI_RTSR_TR13bPEXTI_RTSR_TR14_PosPEXTI_RTSR_TR14_MskPEXTI_RTSR_TR14aPEXTI_RTSR_TR15_PosPEXTI_RTSR_TR15_MskPEXTI_RTSR_TR15`PEXTI_RTSR_TR16_PosPEXTI_RTSR_TR16_MskPEXTI_RTSR_TR16_PEXTI_RTSR_TR17_PosPEXTI_RTSR_TR17_MskPEXTI_RTSR_TR17^PEXTI_RTSR_TR18_PosPEXTI_RTSR_TR18_MskPEXTI_RTSR_TR18]PEXTI_RTSR_RT0PEXTI_RTSR_RT1PEXTI_RTSR_RT2PEXTI_RTSR_RT3PEXTI_RTSR_RT4PEXTI_RTSR_RT5PEXTI_RTSR_RT6PEXTI_RTSR_RT7PEXTI_RTSR_RT8PEXTI_RTSR_RT9PEXTI_RTSR_RT10ePEXTI_RTSR_RT11dPEXTI_RTSR_RT12cPEXTI_RTSR_RT13bPEXTI_RTSR_RT14aPEXTI_RTSR_RT15`PEXTI_RTSR_RT16_PEXTI_RTSR_RT17^PEXTI_RTSR_RT18]PEXTI_FTSR_TR0_Pos PEXTI_FTSR_TR0_MskPEXTI_FTSR_TR0PEXTI_FTSR_TR1_Pos PEXTI_FTSR_TR1_MskPEXTI_FTSR_TR1PEXTI_FTSR_TR2_Pos PEXTI_FTSR_TR2_MskPEXTI_FTSR_TR2PEXTI_FTSR_TR3_PosPEXTI_FTSR_TR3_MskPEXTI_FTSR_TR3PEXTI_FTSR_TR4_PosPEXTI_FTSR_TR4_MskPEXTI_FTSR_TR4PEXTI_FTSR_TR5_PosPEXTI_FTSR_TR5_Msk PEXTI_FTSR_TR5PEXTI_FTSR_TR6_PosPEXTI_FTSR_TR6_Msk PEXTI_FTSR_TR6PEXTI_FTSR_TR7_PosPEXTI_FTSR_TR7_Msk PEXTI_FTSR_TR7PEXTI_FTSR_TR8_PosPEXTI_FTSR_TR8_Msk PEXTI_FTSR_TR8PEXTI_FTSR_TR9_PosPEXTI_FTSR_TR9_Msk PEXTI_FTSR_TR9PEXTI_FTSR_TR10_PosPEXTI_FTSR_TR10_MskPEXTI_FTSR_TR10qPEXTI_FTSR_TR11_PosPEXTI_FTSR_TR11_MskPEXTI_FTSR_TR11pPEXTI_FTSR_TR12_PosPEXTI_FTSR_TR12_MskPEXTI_FTSR_TR12oPEXTI_FTSR_TR13_PosPEXTI_FTSR_TR13_MskPEXTI_FTSR_TR13nPEXTI_FTSR_TR14_PosPEXTI_FTSR_TR14_MskPEXTI_FTSR_TR14mPEXTI_FTSR_TR15_PosPEXTI_FTSR_TR15_MskPEXTI_FTSR_TR15lPEXTI_FTSR_TR16_PosPEXTI_FTSR_TR16_MskPEXTI_FTSR_TR16kPEXTI_FTSR_TR17_PosPEXTI_FTSR_TR17_MskPEXTI_FTSR_TR17jPEXTI_FTSR_TR18_PosPEXTI_FTSR_TR18_MskPEXTI_FTSR_TR18iPEXTI_FTSR_FT0PEXTI_FTSR_FT1PEXTI_FTSR_FT2PEXTI_FTSR_FT3PEXTI_FTSR_FT4PEXTI_FTSR_FT5PEXTI_FTSR_FT6PEXTI_FTSR_FT7PEXTI_FTSR_FT8PEXTI_FTSR_FT9PEXTI_FTSR_FT10}PEXTI_FTSR_FT11|PEXTI_FTSR_FT12{PEXTI_FTSR_FT13zPEXTI_FTSR_FT14yPEXTI_FTSR_FT15xPEXTI_FTSR_FT16wPEXTI_FTSR_FT17vPEXTI_FTSR_FT18uPEXTI_SWIER_SWIER0_PosPEXTI_SWIER_SWIER0_MskPEXTI_SWIER_SWIER0mPEXTI_SWIER_SWIER1_PosPEXTI_SWIER_SWIER1_MskPEXTI_SWIER_SWIER1lPEXTI_SWIER_SWIER2_PosPEXTI_SWIER_SWIER2_MskPEXTI_SWIER_SWIER2kPEXTI_SWIER_SWIER3_PosPEXTI_SWIER_SWIER3_MskPEXTI_SWIER_SWIER3jPEXTI_SWIER_SWIER4_PosPEXTI_SWIER_SWIER4_MskPEXTI_SWIER_SWIER4iPEXTI_SWIER_SWIER5_PosPEXTI_SWIER_SWIER5_MskPEXTI_SWIER_SWIER5hPEXTI_SWIER_SWIER6_PosPEXTI_SWIER_SWIER6_MskPEXTI_SWIER_SWIER6gPEXTI_SWIER_SWIER7_PosPEXTI_SWIER_SWIER7_MskPEXTI_SWIER_SWIER7fPEXTI_SWIER_SWIER8_PosPEXTI_SWIER_SWIER8_MskPEXTI_SWIER_SWIER8ePEXTI_SWIER_SWIER9_PosPEXTI_SWIER_SWIER9_MskPEXTI_SWIER_SWIER9dPEXTI_SWIER_SWIER10_PosPEXTI_SWIER_SWIER10_MskPEXTI_SWIER_SWIER10:PEXTI_SWIER_SWIER11_PosPEXTI_SWIER_SWIER11_MskPEXTI_SWIER_SWIER119PEXTI_SWIER_SWIER12_PosPEXTI_SWIER_SWIER12_MskPEXTI_SWIER_SWIER128PEXTI_SWIER_SWIER13_PosPEXTI_SWIER_SWIER13_MskPEXTI_SWIER_SWIER137PEXTI_SWIER_SWIER14_PosPEXTI_SWIER_SWIER14_MskPEXTI_SWIER_SWIER146PEXTI_SWIER_SWIER15_PosPEXTI_SWIER_SWIER15_MskPEXTI_SWIER_SWIER155PEXTI_SWIER_SWIER16_PosPEXTI_SWIER_SWIER16_MskPEXTI_SWIER_SWIER164PEXTI_SWIER_SWIER17_PosPEXTI_SWIER_SWIER17_MskPEXTI_SWIER_SWIER173PEXTI_SWIER_SWIER18_PosPEXTI_SWIER_SWIER18_MskPEXTI_SWIER_SWIER182PEXTI_SWIER_SWI0PEXTI_SWIER_SWI1PEXTI_SWIER_SWI2PEXTI_SWIER_SWI3PEXTI_SWIER_SWI4PEXTI_SWIER_SWI5PEXTI_SWIER_SWI6PEXTI_SWIER_SWI7PEXTI_SWIER_SWI8PEXTI_SWIER_SWI9PEXTI_SWIER_SWI10PEXTI_SWIER_SWI11PEXTI_SWIER_SWI12PEXTI_SWIER_SWI13PEXTI_SWIER_SWI14PEXTI_SWIER_SWI15PEXTI_SWIER_SWI16PEXTI_SWIER_SWI17PEXTI_SWIER_SWI18PEXTI_PR_PR0_PosPEXTI_PR_PR0_MskP EXTI_PR_PR0IPEXTI_PR_PR1_PosPEXTI_PR_PR1_MskP EXTI_PR_PR1HPEXTI_PR_PR2_PosPEXTI_PR_PR2_MskP EXTI_PR_PR2GPEXTI_PR_PR3_PosPEXTI_PR_PR3_MskP EXTI_PR_PR3FPEXTI_PR_PR4_PosPEXTI_PR_PR4_MskP EXTI_PR_PR4EPEXTI_PR_PR5_PosPEXTI_PR_PR5_MskP EXTI_PR_PR5DPEXTI_PR_PR6_PosPEXTI_PR_PR6_MskP EXTI_PR_PR6CPEXTI_PR_PR7_PosPEXTI_PR_PR7_MskP EXTI_PR_PR7BPEXTI_PR_PR8_PosPEXTI_PR_PR8_MskP EXTI_PR_PR8APEXTI_PR_PR9_PosPEXTI_PR_PR9_MskP EXTI_PR_PR9@PEXTI_PR_PR10_Pos}PEXTI_PR_PR10_MskP EXTI_PR_PR10PEXTI_PR_PR11_Pos|PEXTI_PR_PR11_MskP EXTI_PR_PR11PEXTI_PR_PR12_Pos{PEXTI_PR_PR12_MskP EXTI_PR_PR12PEXTI_PR_PR13_PoszPEXTI_PR_PR13_MskP EXTI_PR_PR13PEXTI_PR_PR14_PosyPEXTI_PR_PR14_MskP EXTI_PR_PR14PEXTI_PR_PR15_PosxPEXTI_PR_PR15_MskP EXTI_PR_PR15PEXTI_PR_PR16_PoswPEXTI_PR_PR16_Msk~P EXTI_PR_PR16PEXTI_PR_PR17_PosvPEXTI_PR_PR17_Msk}P EXTI_PR_PR17PEXTI_PR_PR18_PosuPEXTI_PR_PR18_Msk|P EXTI_PR_PR18P EXTI_PR_PIF0 P EXTI_PR_PIF1 P EXTI_PR_PIF2P EXTI_PR_PIF3P EXTI_PR_PIF4P EXTI_PR_PIF5P EXTI_PR_PIF6P EXTI_PR_PIF7P EXTI_PR_PIF8P EXTI_PR_PIF9PEXTI_PR_PIF10PEXTI_PR_PIF11PEXTI_PR_PIF12PEXTI_PR_PIF13PEXTI_PR_PIF14PEXTI_PR_PIF15PEXTI_PR_PIF16PEXTI_PR_PIF17PEXTI_PR_PIF18PDMA_ISR_GIF1_PosPDMA_ISR_GIF1_MskP DMA_ISR_GIF1.PDMA_ISR_TCIF1_PosCPDMA_ISR_TCIF1_MskJPDMA_ISR_TCIF1PDMA_ISR_HTIF1_Pos>PDMA_ISR_HTIF1_MskEPDMA_ISR_HTIF1PDMA_ISR_TEIF1_PosAPDMA_ISR_TEIF1_MskHPDMA_ISR_TEIF1PDMA_ISR_GIF2_PosPDMA_ISR_GIF2_MskP DMA_ISR_GIF2-PDMA_ISR_TCIF2_PosBPDMA_ISR_TCIF2_MskIPDMA_ISR_TCIF2PDMA_ISR_HTIF2_Pos=PDMA_ISR_HTIF2_MskDPDMA_ISR_HTIF2PDMA_ISR_TEIF2_Pos@PDMA_ISR_TEIF2_MskGPDMA_ISR_TEIF2PDMA_ISR_GIF3_PosPDMA_ISR_GIF3_MskP DMA_ISR_GIF3,PDMA_ISR_TCIF3_PosAPDMA_ISR_TCIF3_MskHPDMA_ISR_TCIF3PDMA_ISR_HTIF3_Pos<PDMA_ISR_HTIF3_MskCPDMA_ISR_HTIF3PDMA_ISR_TEIF3_Pos?PDMA_ISR_TEIF3_MskFPDMA_ISR_TEIF3PDMA_ISR_GIF4_PosPDMA_ISR_GIF4_MskP DMA_ISR_GIF4+PDMA_ISR_TCIF4_Pos@PDMA_ISR_TCIF4_MskGPDMA_ISR_TCIF4PDMA_ISR_HTIF4_Pos;PDMA_ISR_HTIF4_MskBPDMA_ISR_HTIF4PDMA_ISR_TEIF4_Pos>PDMA_ISR_TEIF4_MskEPDMA_ISR_TEIF4PDMA_ISR_GIF5_PosPDMA_ISR_GIF5_MskP DMA_ISR_GIF5*PDMA_ISR_TCIF5_Pos?PDMA_ISR_TCIF5_MskFPDMA_ISR_TCIF5PDMA_ISR_HTIF5_Pos:PDMA_ISR_HTIF5_MskAPDMA_ISR_HTIF5PDMA_ISR_TEIF5_Pos=PDMA_ISR_TEIF5_MskDPDMA_ISR_TEIF5PDMA_ISR_GIF6_PosPDMA_ISR_GIF6_MskP DMA_ISR_GIF6)PDMA_ISR_TCIF6_Pos>PDMA_ISR_TCIF6_MskEPDMA_ISR_TCIF6PDMA_ISR_HTIF6_Pos9PDMA_ISR_HTIF6_Msk@PDMA_ISR_HTIF6PDMA_ISR_TEIF6_Pos<PDMA_ISR_TEIF6_MskCPDMA_ISR_TEIF6PDMA_ISR_GIF7_PosPDMA_ISR_GIF7_MskP DMA_ISR_GIF7(PDMA_ISR_TCIF7_Pos=PDMA_ISR_TCIF7_MskDPDMA_ISR_TCIF7PDMA_ISR_HTIF7_Pos8PDMA_ISR_HTIF7_Msk?PDMA_ISR_HTIF7PDMA_ISR_TEIF7_Pos;PDMA_ISR_TEIF7_MskBPDMA_ISR_TEIF7PDMA_IFCR_CGIF1_PosPDMA_IFCR_CGIF1_MskPDMA_IFCR_CGIF1PDMA_IFCR_CTCIF1_PosPDMA_IFCR_CTCIF1_MskPDMA_IFCR_CTCIF1_PDMA_IFCR_CHTIF1_PosPDMA_IFCR_CHTIF1_MskPDMA_IFCR_CHTIF1ZPDMA_IFCR_CTEIF1_PosPDMA_IFCR_CTEIF1_MskPDMA_IFCR_CTEIF1]PDMA_IFCR_CGIF2_PosPDMA_IFCR_CGIF2_MskPDMA_IFCR_CGIF2PDMA_IFCR_CTCIF2_PosPDMA_IFCR_CTCIF2_MskPDMA_IFCR_CTCIF2^PDMA_IFCR_CHTIF2_PosPDMA_IFCR_CHTIF2_MskPDMA_IFCR_CHTIF2YPDMA_IFCR_CTEIF2_PosPDMA_IFCR_CTEIF2_MskPDMA_IFCR_CTEIF2\PDMA_IFCR_CGIF3_PosPDMA_IFCR_CGIF3_MskPDMA_IFCR_CGIF3PDMA_IFCR_CTCIF3_PosPDMA_IFCR_CTCIF3_MskPDMA_IFCR_CTCIF3]PDMA_IFCR_CHTIF3_PosPDMA_IFCR_CHTIF3_MskPDMA_IFCR_CHTIF3XPDMA_IFCR_CTEIF3_PosPDMA_IFCR_CTEIF3_MskPDMA_IFCR_CTEIF3[PDMA_IFCR_CGIF4_PosPDMA_IFCR_CGIF4_MskPDMA_IFCR_CGIF4PDMA_IFCR_CTCIF4_PosPDMA_IFCR_CTCIF4_MskPDMA_IFCR_CTCIF4\PDMA_IFCR_CHTIF4_PosPDMA_IFCR_CHTIF4_MskPDMA_IFCR_CHTIF4WPDMA_IFCR_CTEIF4_PosPDMA_IFCR_CTEIF4_MskPDMA_IFCR_CTEIF4ZPDMA_IFCR_CGIF5_PosPDMA_IFCR_CGIF5_MskPDMA_IFCR_CGIF5PDMA_IFCR_CTCIF5_PosPDMA_IFCR_CTCIF5_MskPDMA_IFCR_CTCIF5[PDMA_IFCR_CHTIF5_PosPDMA_IFCR_CHTIF5_MskPDMA_IFCR_CHTIF5VPDMA_IFCR_CTEIF5_PosPDMA_IFCR_CTEIF5_MskPDMA_IFCR_CTEIF5YPDMA_IFCR_CGIF6_PosPDMA_IFCR_CGIF6_MskPDMA_IFCR_CGIF6PDMA_IFCR_CTCIF6_PosPDMA_IFCR_CTCIF6_MskPDMA_IFCR_CTCIF6ZPDMA_IFCR_CHTIF6_PosPDMA_IFCR_CHTIF6_MskPDMA_IFCR_CHTIF6UPDMA_IFCR_CTEIF6_PosPDMA_IFCR_CTEIF6_MskPDMA_IFCR_CTEIF6XPDMA_IFCR_CGIF7_PosPDMA_IFCR_CGIF7_MskPDMA_IFCR_CGIF7PDMA_IFCR_CTCIF7_PosPDMA_IFCR_CTCIF7_MskPDMA_IFCR_CTCIF7YPDMA_IFCR_CHTIF7_PosPDMA_IFCR_CHTIF7_MskPDMA_IFCR_CHTIF7TPDMA_IFCR_CTEIF7_PosPDMA_IFCR_CTEIF7_MskPDMA_IFCR_CTEIF7WPDMA_CCR_EN_Pos#PDMA_CCR_EN_Msk*P DMA_CCR_ENPDMA_CCR_TCIE_PosPDMA_CCR_TCIE_MskP DMA_CCR_TCIE&PDMA_CCR_HTIE_PosPDMA_CCR_HTIE_MskP DMA_CCR_HTIE!PDMA_CCR_TEIE_PosPDMA_CCR_TEIE_MskP DMA_CCR_TEIE$PDMA_CCR_DIR_PosPDMA_CCR_DIR_MskP DMA_CCR_DIRnPDMA_CCR_CIRC_PosPDMA_CCR_CIRC_MskP DMA_CCR_CIRC*PDMA_CCR_PINC_PosPDMA_CCR_PINC_MskP DMA_CCR_PINC!PDMA_CCR_MINC_PosPDMA_CCR_MINC_MskP DMA_CCR_MINC$PDMA_CCR_PSIZE_Pos%PDMA_CCR_PSIZE_Msk,PDMA_CCR_PSIZEPDMA_CCR_PSIZE_0+PDMA_CCR_PSIZE_1*PDMA_CCR_MSIZE_Pos(PDMA_CCR_MSIZE_Msk/PDMA_CCR_MSIZEPDMA_CCR_MSIZE_0.PDMA_CCR_MSIZE_1-PDMA_CCR_PL_PosPDMA_CCR_PL_Msk!P DMA_CCR_PLP DMA_CCR_PL_0 P DMA_CCR_PL_1PDMA_CCR_MEM2MEM_PosPDMA_CCR_MEM2MEM_MskPDMA_CCR_MEM2MEMUPDMA_CNDTR_NDT_Pos'PDMA_CNDTR_NDT_Msk.PDMA_CNDTR_NDTPDMA_CPAR_PA_PosPDMA_CPAR_PA_MskP DMA_CPAR_PAnPDMA_CMAR_MA_PosPDMA_CMAR_MA_MskP DMA_CMAR_MAtPADC_MULTIMODE_SUPPORT.PADC_SR_AWD_PosPADC_SR_AWD_MskP ADC_SR_AWDPADC_SR_EOS_Pos PADC_SR_EOS_MskP ADC_SR_EOSPADC_SR_JEOS_PosPADC_SR_JEOS_MskP ADC_SR_JEOSYPADC_SR_JSTRT_PosXPADC_SR_JSTRT_Msk_P ADC_SR_JSTRTPADC_SR_STRT_PosPADC_SR_STRT_MskP ADC_SR_STRT=P ADC_SR_EOCP ADC_SR_JEOCiPADC_CR1_AWDCH_PosePADC_CR1_AWDCH_MsklPADC_CR1_AWDCHPADC_CR1_AWDCH_0kPADC_CR1_AWDCH_1jPADC_CR1_AWDCH_2iPADC_CR1_AWDCH_3hPADC_CR1_AWDCH_4gPADC_CR1_EOSIE_PosWPADC_CR1_EOSIE_Msk^PADC_CR1_EOSIEPADC_CR1_AWDIE_PosbPADC_CR1_AWDIE_MskiPADC_CR1_AWDIEPADC_CR1_JEOSIE_Pos PADC_CR1_JEOSIE_MskPADC_CR1_JEOSIEPADC_CR1_SCAN_PosPADC_CR1_SCAN_MskP ADC_CR1_SCANBPADC_CR1_AWDSGL_PosPADC_CR1_AWDSGL_MskPADC_CR1_AWDSGLPADC_CR1_JAUTO_PosIPADC_CR1_JAUTO_MskPPADC_CR1_JAUTOPADC_CR1_DISCEN_PosPADC_CR1_DISCEN_MskPADC_CR1_DISCENPADC_CR1_JDISCEN_PosPADC_CR1_JDISCEN_MskPADC_CR1_JDISCENaPADC_CR1_DISCNUM_PosPADC_CR1_DISCNUM_MskPADC_CR1_DISCNUMNPADC_CR1_DISCNUM_0PADC_CR1_DISCNUM_1PADC_CR1_DISCNUM_2PADC_CR1_DUALMOD_PosPADC_CR1_DUALMOD_MskPADC_CR1_DUALMOD[PADC_CR1_DUALMOD_0PADC_CR1_DUALMOD_1PADC_CR1_DUALMOD_2PADC_CR1_DUALMOD_3PADC_CR1_JAWDEN_PosPADC_CR1_JAWDEN_MskPADC_CR1_JAWDENPADC_CR1_AWDEN_Pos]PADC_CR1_AWDEN_MskdPADC_CR1_AWDENPADC_CR1_EOCIEPADC_CR1_JEOCIEPADC_CR2_ADON_PosPADC_CR2_ADON_MskP ADC_CR2_ADONDPADC_CR2_CONT_PosPADC_CR2_CONT_MskP ADC_CR2_CONT2PADC_CR2_CAL_PosPADC_CR2_CAL_MskP ADC_CR2_CALPADC_CR2_RSTCAL_PosPADC_CR2_RSTCAL_MskPADC_CR2_RSTCALPADC_CR2_DMA_PosPADC_CR2_DMA_MskP ADC_CR2_DMAPADC_CR2_ALIGN_Pos`PADC_CR2_ALIGN_MskgPADC_CR2_ALIGNPADC_CR2_JEXTSEL_PosPADC_CR2_JEXTSEL_MskPADC_CR2_JEXTSELAPADC_CR2_JEXTSEL_0PADC_CR2_JEXTSEL_1PADC_CR2_JEXTSEL_2PADC_CR2_JEXTTRIG_PosTPADC_CR2_JEXTTRIG_Msk[PADC_CR2_JEXTTRIGPADC_CR2_EXTSEL_PosPADC_CR2_EXTSEL_MskPADC_CR2_EXTSELPADC_CR2_EXTSEL_0PADC_CR2_EXTSEL_1PADC_CR2_EXTSEL_2PADC_CR2_EXTTRIG_PosPADC_CR2_EXTTRIG_MskPADC_CR2_EXTTRIG9PADC_CR2_JSWSTART_PosCPADC_CR2_JSWSTART_MskJPADC_CR2_JSWSTARTPADC_CR2_SWSTART_PosPADC_CR2_SWSTART_MskPADC_CR2_SWSTART(PADC_CR2_TSVREFE_PosPADC_CR2_TSVREFE_MskPADC_CR2_TSVREFEAPADC_SMPR1_SMP10_PosPADC_SMPR1_SMP10_MskPADC_SMPR1_SMP10cPADC_SMPR1_SMP10_0PADC_SMPR1_SMP10_1PADC_SMPR1_SMP10_2PADC_SMPR1_SMP11_PosPADC_SMPR1_SMP11_MskPADC_SMPR1_SMP11bPADC_SMPR1_SMP11_0PADC_SMPR1_SMP11_1PADC_SMPR1_SMP11_2PADC_SMPR1_SMP12_PosPADC_SMPR1_SMP12_MskPADC_SMPR1_SMP12aPADC_SMPR1_SMP12_0PADC_SMPR1_SMP12_1PADC_SMPR1_SMP12_2PADC_SMPR1_SMP13_PosPADC_SMPR1_SMP13_MskPADC_SMPR1_SMP13`PADC_SMPR1_SMP13_0PADC_SMPR1_SMP13_1PADC_SMPR1_SMP13_2PADC_SMPR1_SMP14_PosPADC_SMPR1_SMP14_MskPADC_SMPR1_SMP14_PADC_SMPR1_SMP14_0PADC_SMPR1_SMP14_1PADC_SMPR1_SMP14_2PADC_SMPR1_SMP15_PosPADC_SMPR1_SMP15_MskPADC_SMPR1_SMP15^PADC_SMPR1_SMP15_0PADC_SMPR1_SMP15_1PADC_SMPR1_SMP15_2PADC_SMPR1_SMP16_PosPADC_SMPR1_SMP16_MskPADC_SMPR1_SMP16]PADC_SMPR1_SMP16_0PADC_SMPR1_SMP16_1PADC_SMPR1_SMP16_2PADC_SMPR1_SMP17_PosPADC_SMPR1_SMP17_MskPADC_SMPR1_SMP17\PADC_SMPR1_SMP17_0PADC_SMPR1_SMP17_1PADC_SMPR1_SMP17_2PADC_SMPR2_SMP0_PosPADC_SMPR2_SMP0_MskPADC_SMPR2_SMP0PADC_SMPR2_SMP0_0PADC_SMPR2_SMP0_1PADC_SMPR2_SMP0_2PADC_SMPR2_SMP1_PosPADC_SMPR2_SMP1_MskPADC_SMPR2_SMP1PADC_SMPR2_SMP1_0PADC_SMPR2_SMP1_1PADC_SMPR2_SMP1_2PADC_SMPR2_SMP2_PosPADC_SMPR2_SMP2_MskPADC_SMPR2_SMP2PADC_SMPR2_SMP2_0PADC_SMPR2_SMP2_1PADC_SMPR2_SMP2_2PADC_SMPR2_SMP3_PosPADC_SMPR2_SMP3_MskPADC_SMPR2_SMP3PADC_SMPR2_SMP3_0PADC_SMPR2_SMP3_1PADC_SMPR2_SMP3_2PADC_SMPR2_SMP4_PosPADC_SMPR2_SMP4_MskPADC_SMPR2_SMP4PADC_SMPR2_SMP4_0PADC_SMPR2_SMP4_1PADC_SMPR2_SMP4_2PADC_SMPR2_SMP5_PosPADC_SMPR2_SMP5_MskPADC_SMPR2_SMP5PADC_SMPR2_SMP5_0PADC_SMPR2_SMP5_1PADC_SMPR2_SMP5_2PADC_SMPR2_SMP6_PosPADC_SMPR2_SMP6_MskPADC_SMPR2_SMP6PADC_SMPR2_SMP6_0PADC_SMPR2_SMP6_1PADC_SMPR2_SMP6_2PADC_SMPR2_SMP7_PosPADC_SMPR2_SMP7_MskPADC_SMPR2_SMP7PADC_SMPR2_SMP7_0PADC_SMPR2_SMP7_1PADC_SMPR2_SMP7_2PADC_SMPR2_SMP8_PosPADC_SMPR2_SMP8_MskPADC_SMPR2_SMP8PADC_SMPR2_SMP8_0PADC_SMPR2_SMP8_1PADC_SMPR2_SMP8_2PADC_SMPR2_SMP9_PosPADC_SMPR2_SMP9_MskPADC_SMPR2_SMP9PADC_SMPR2_SMP9_0PADC_SMPR2_SMP9_1PADC_SMPR2_SMP9_2PADC_JOFR1_JOFFSET1_PosPADC_JOFR1_JOFFSET1_MskPADC_JOFR1_JOFFSET1}PADC_JOFR2_JOFFSET2_PosPADC_JOFR2_JOFFSET2_MskPADC_JOFR2_JOFFSET2{PADC_JOFR3_JOFFSET3_PosPADC_JOFR3_JOFFSET3_MskPADC_JOFR3_JOFFSET3yPADC_JOFR4_JOFFSET4_PosPADC_JOFR4_JOFFSET4_MskPADC_JOFR4_JOFFSET4wPADC_HTR_HT_PosPADC_HTR_HT_MskP ADC_HTR_HTPADC_LTR_LT_PosPADC_LTR_LT_Msk P ADC_LTR_LTPADC_SQR1_SQ13_PoscPADC_SQR1_SQ13_MskjPADC_SQR1_SQ13PADC_SQR1_SQ13_0iPADC_SQR1_SQ13_1hPADC_SQR1_SQ13_2gPADC_SQR1_SQ13_3fPADC_SQR1_SQ13_4ePADC_SQR1_SQ14_PosbPADC_SQR1_SQ14_MskiPADC_SQR1_SQ14PADC_SQR1_SQ14_0hPADC_SQR1_SQ14_1gPADC_SQR1_SQ14_2fPADC_SQR1_SQ14_3ePADC_SQR1_SQ14_4dPADC_SQR1_SQ15_PosaPADC_SQR1_SQ15_MskhPADC_SQR1_SQ15PADC_SQR1_SQ15_0gPADC_SQR1_SQ15_1fPADC_SQR1_SQ15_2ePADC_SQR1_SQ15_3dPADC_SQR1_SQ15_4cPADC_SQR1_SQ16_Pos`PADC_SQR1_SQ16_MskgPADC_SQR1_SQ16PADC_SQR1_SQ16_0fPADC_SQR1_SQ16_1ePADC_SQR1_SQ16_2dPADC_SQR1_SQ16_3cPADC_SQR1_SQ16_4bPADC_SQR1_L_Pos%PADC_SQR1_L_Msk,P ADC_SQR1_LP ADC_SQR1_L_0+P ADC_SQR1_L_1*P ADC_SQR1_L_2)P ADC_SQR1_L_3(PADC_SQR2_SQ7_PosPADC_SQR2_SQ7_MskP ADC_SQR2_SQ7*PADC_SQR2_SQ7_0PADC_SQR2_SQ7_1PADC_SQR2_SQ7_2PADC_SQR2_SQ7_3PADC_SQR2_SQ7_4PADC_SQR2_SQ8_PosPADC_SQR2_SQ8_MskP ADC_SQR2_SQ8)PADC_SQR2_SQ8_0PADC_SQR2_SQ8_1PADC_SQR2_SQ8_2PADC_SQR2_SQ8_3PADC_SQR2_SQ8_4PADC_SQR2_SQ9_PosPADC_SQR2_SQ9_MskP ADC_SQR2_SQ9(PADC_SQR2_SQ9_0PADC_SQR2_SQ9_1PADC_SQR2_SQ9_2PADC_SQR2_SQ9_3PADC_SQR2_SQ9_4PADC_SQR2_SQ10_PosePADC_SQR2_SQ10_MsklPADC_SQR2_SQ10PADC_SQR2_SQ10_0kPADC_SQR2_SQ10_1jPADC_SQR2_SQ10_2iPADC_SQR2_SQ10_3hPADC_SQR2_SQ10_4gPADC_SQR2_SQ11_PosdPADC_SQR2_SQ11_MskkPADC_SQR2_SQ11PADC_SQR2_SQ11_0jPADC_SQR2_SQ11_1iPADC_SQR2_SQ11_2hPADC_SQR2_SQ11_3gPADC_SQR2_SQ11_4fPADC_SQR2_SQ12_PoscPADC_SQR2_SQ12_MskjPADC_SQR2_SQ12PADC_SQR2_SQ12_0iPADC_SQR2_SQ12_1hPADC_SQR2_SQ12_2gPADC_SQR2_SQ12_3fPADC_SQR2_SQ12_4ePADC_SQR3_SQ1_PosPADC_SQR3_SQ1_MskP ADC_SQR3_SQ1/PADC_SQR3_SQ1_0PADC_SQR3_SQ1_1PADC_SQR3_SQ1_2PADC_SQR3_SQ1_3PADC_SQR3_SQ1_4PADC_SQR3_SQ2_PosPADC_SQR3_SQ2_MskP ADC_SQR3_SQ2.PADC_SQR3_SQ2_0PADC_SQR3_SQ2_1PADC_SQR3_SQ2_2PADC_SQR3_SQ2_3PADC_SQR3_SQ2_4PADC_SQR3_SQ3_PosPADC_SQR3_SQ3_MskP ADC_SQR3_SQ3-PADC_SQR3_SQ3_0PADC_SQR3_SQ3_1PADC_SQR3_SQ3_2PADC_SQR3_SQ3_3PADC_SQR3_SQ3_4PADC_SQR3_SQ4_PosPADC_SQR3_SQ4_MskP ADC_SQR3_SQ4,PADC_SQR3_SQ4_0PADC_SQR3_SQ4_1PADC_SQR3_SQ4_2PADC_SQR3_SQ4_3PADC_SQR3_SQ4_4PADC_SQR3_SQ5_PosPADC_SQR3_SQ5_MskP ADC_SQR3_SQ5+PADC_SQR3_SQ5_0PADC_SQR3_SQ5_1PADC_SQR3_SQ5_2PADC_SQR3_SQ5_3PADC_SQR3_SQ5_4PADC_SQR3_SQ6_PosPADC_SQR3_SQ6_MskP ADC_SQR3_SQ6*PADC_SQR3_SQ6_0PADC_SQR3_SQ6_1PADC_SQR3_SQ6_2PADC_SQR3_SQ6_3PADC_SQR3_SQ6_4PADC_JSQR_JSQ1_Pos3PADC_JSQR_JSQ1_Msk:PADC_JSQR_JSQ1PADC_JSQR_JSQ1_09PADC_JSQR_JSQ1_18PADC_JSQR_JSQ1_27PADC_JSQR_JSQ1_36PADC_JSQR_JSQ1_45PADC_JSQR_JSQ2_Pos2PADC_JSQR_JSQ2_Msk9PADC_JSQR_JSQ2PADC_JSQR_JSQ2_08PADC_JSQR_JSQ2_17PADC_JSQR_JSQ2_26PADC_JSQR_JSQ2_35PADC_JSQR_JSQ2_44PADC_JSQR_JSQ3_Pos1PADC_JSQR_JSQ3_Msk8PADC_JSQR_JSQ3PADC_JSQR_JSQ3_07PADC_JSQR_JSQ3_16PADC_JSQR_JSQ3_25PADC_JSQR_JSQ3_34PADC_JSQR_JSQ3_43PADC_JSQR_JSQ4_Pos0PADC_JSQR_JSQ4_Msk7PADC_JSQR_JSQ4PADC_JSQR_JSQ4_06PADC_JSQR_JSQ4_15PADC_JSQR_JSQ4_24PADC_JSQR_JSQ4_33PADC_JSQR_JSQ4_42PADC_JSQR_JL_PosPADC_JSQR_JL_MskP ADC_JSQR_JLYPADC_JSQR_JL_0PADC_JSQR_JL_1PADC_JDR1_JDATA_PosPADC_JDR1_JDATA_Msk"PADC_JDR1_JDATAPADC_JDR2_JDATA_PosPADC_JDR2_JDATA_Msk!PADC_JDR2_JDATAPADC_JDR3_JDATA_PosPADC_JDR3_JDATA_Msk PADC_JDR3_JDATAPADC_JDR4_JDATA_PosPADC_JDR4_JDATA_MskPADC_JDR4_JDATAPADC_DR_DATA_PosPADC_DR_DATA_MskP ADC_DR_DATAPADC_DR_ADC2DATA_PosPADC_DR_ADC2DATA_MskPADC_DR_ADC2DATA}PDAC_CR_EN1_Pos?PDAC_CR_EN1_MskFP DAC_CR_EN1PDAC_CR_BOFF1_PosPDAC_CR_BOFF1_MskP DAC_CR_BOFF1JPDAC_CR_TEN1_PosPDAC_CR_TEN1_MskP DAC_CR_TEN1PDAC_CR_TSEL1_PosPDAC_CR_TSEL1_MskP DAC_CR_TSEL1/PDAC_CR_TSEL1_0PDAC_CR_TSEL1_1PDAC_CR_TSEL1_2PDAC_CR_WAVE1_PosPDAC_CR_WAVE1_MskP DAC_CR_WAVE14PDAC_CR_WAVE1_0PDAC_CR_WAVE1_1PDAC_CR_MAMP1_PosPDAC_CR_MAMP1_MskP DAC_CR_MAMP1<PDAC_CR_MAMP1_0PDAC_CR_MAMP1_1PDAC_CR_MAMP1_2PDAC_CR_MAMP1_3PDAC_CR_DMAEN1_PosgPDAC_CR_DMAEN1_MsknPDAC_CR_DMAEN1PDAC_CR_EN2_Pos>PDAC_CR_EN2_MskEP DAC_CR_EN2PDAC_CR_BOFF2_PosPDAC_CR_BOFF2_MskP DAC_CR_BOFF2IPDAC_CR_TEN2_PosPDAC_CR_TEN2_MskP DAC_CR_TEN2PDAC_CR_TSEL2_PosPDAC_CR_TSEL2_MskP DAC_CR_TSEL2.PDAC_CR_TSEL2_0PDAC_CR_TSEL2_1PDAC_CR_TSEL2_2PDAC_CR_WAVE2_PosPDAC_CR_WAVE2_MskP DAC_CR_WAVE23PDAC_CR_WAVE2_0PDAC_CR_WAVE2_1PDAC_CR_MAMP2_PosPDAC_CR_MAMP2_MskP DAC_CR_MAMP2;PDAC_CR_MAMP2_0PDAC_CR_MAMP2_1PDAC_CR_MAMP2_2PDAC_CR_MAMP2_3PDAC_CR_DMAEN2_PosfPDAC_CR_DMAEN2_MskmPDAC_CR_DMAEN2 PDAC_SWTRIGR_SWTRIG1_PosC PDAC_SWTRIGR_SWTRIG1_MskJPDAC_SWTRIGR_SWTRIG1 PDAC_SWTRIGR_SWTRIG2_PosB PDAC_SWTRIGR_SWTRIG2_MskIPDAC_SWTRIGR_SWTRIG2!PDAC_DHR12R1_DACC1DHR_Pos!PDAC_DHR12R1_DACC1DHR_MskPDAC_DHR12R1_DACC1DHR?!PDAC_DHR12L1_DACC1DHR_Pos!PDAC_DHR12L1_DACC1DHR_MskPDAC_DHR12L1_DACC1DHRE PDAC_DHR8R1_DACC1DHR_Pos PDAC_DHR8R1_DACC1DHR_MskPDAC_DHR8R1_DACC1DHRl!PDAC_DHR12R2_DACC2DHR_Pos!PDAC_DHR12R2_DACC2DHR_MskPDAC_DHR12R2_DACC2DHR=!PDAC_DHR12L2_DACC2DHR_Pos!PDAC_DHR12L2_DACC2DHR_MskPDAC_DHR12L2_DACC2DHRC PDAC_DHR8R2_DACC2DHR_Pos PDAC_DHR8R2_DACC2DHR_MskPDAC_DHR8R2_DACC2DHRj!PDAC_DHR12RD_DACC1DHR_Pos!PDAC_DHR12RD_DACC1DHR_MskPDAC_DHR12RD_DACC1DHR,!PDAC_DHR12RD_DACC2DHR_Pos!PDAC_DHR12RD_DACC2DHR_MskPDAC_DHR12RD_DACC2DHR+!PDAC_DHR12LD_DACC1DHR_Pos!PDAC_DHR12LD_DACC1DHR_MskPDAC_DHR12LD_DACC1DHR2!PDAC_DHR12LD_DACC2DHR_Pos!PDAC_DHR12LD_DACC2DHR_MskPDAC_DHR12LD_DACC2DHR1 PDAC_DHR8RD_DACC1DHR_Pos PDAC_DHR8RD_DACC1DHR_MskPDAC_DHR8RD_DACC1DHRY PDAC_DHR8RD_DACC2DHR_Pos PDAC_DHR8RD_DACC2DHR_MskPDAC_DHR8RD_DACC2DHRXPDAC_DOR1_DACC1DOR_PosSPDAC_DOR1_DACC1DOR_MskZPDAC_DOR1_DACC1DORPDAC_DOR2_DACC2DOR_PosQPDAC_DOR2_DACC2DOR_MskXPDAC_DOR2_DACC2DORPTIM_CR1_CEN_PosPTIM_CR1_CEN_MskP TIM_CR1_CENqPTIM_CR1_UDIS_PoswPTIM_CR1_UDIS_Msk~P TIM_CR1_UDISPTIM_CR1_URS_PosPTIM_CR1_URS_MskP TIM_CR1_URSMPTIM_CR1_OPM_PosPTIM_CR1_OPM_MskP TIM_CR1_OPM[PTIM_CR1_DIR_PosPTIM_CR1_DIR_MskP TIM_CR1_DIRhPTIM_CR1_CMS_PosPTIM_CR1_CMS_MskP TIM_CR1_CMSdPTIM_CR1_CMS_0PTIM_CR1_CMS_1PTIM_CR1_ARPE_PosPTIM_CR1_ARPE_MskP TIM_CR1_ARPEPTIM_CR1_CKD_PosPTIM_CR1_CKD_MskP TIM_CR1_CKDuPTIM_CR1_CKD_0PTIM_CR1_CKD_1PTIM_CR2_CCPC_PosPTIM_CR2_CCPC_MskP TIM_CR2_CCPC+PTIM_CR2_CCUS_Pos}PTIM_CR2_CCUS_MskP TIM_CR2_CCUSPTIM_CR2_CCDS_PosPTIM_CR2_CCDS_MskP TIM_CR2_CCDS'PTIM_CR2_MMS_PosPTIM_CR2_MMS_MskP TIM_CR2_MMSYPTIM_CR2_MMS_0PTIM_CR2_MMS_1PTIM_CR2_MMS_2PTIM_CR2_TI1S_PosPTIM_CR2_TI1S_MskP TIM_CR2_TI1S#PTIM_CR2_OIS1_PosPTIM_CR2_OIS1_MskP TIM_CR2_OIS1(PTIM_CR2_OIS1N_Pos?PTIM_CR2_OIS1N_MskFPTIM_CR2_OIS1NPTIM_CR2_OIS2_PosPTIM_CR2_OIS2_MskP TIM_CR2_OIS2'PTIM_CR2_OIS2N_Pos>PTIM_CR2_OIS2N_MskEPTIM_CR2_OIS2NPTIM_CR2_OIS3_PosPTIM_CR2_OIS3_MskP TIM_CR2_OIS3&PTIM_CR2_OIS3N_Pos=PTIM_CR2_OIS3N_MskDPTIM_CR2_OIS3NPTIM_CR2_OIS4_PosPTIM_CR2_OIS4_MskP TIM_CR2_OIS4%PTIM_SMCR_SMS_PosJPTIM_SMCR_SMS_MskQP TIM_SMCR_SMSPTIM_SMCR_SMS_0PPTIM_SMCR_SMS_1OPTIM_SMCR_SMS_2NPTIM_SMCR_TS_PosPTIM_SMCR_TS_MskP TIM_SMCR_TS1PTIM_SMCR_TS_0PTIM_SMCR_TS_1PTIM_SMCR_TS_2PTIM_SMCR_MSM_PosPPTIM_SMCR_MSM_MskWP TIM_SMCR_MSMPTIM_SMCR_ETF_Pos^PTIM_SMCR_ETF_MskeP TIM_SMCR_ETFPTIM_SMCR_ETF_0dPTIM_SMCR_ETF_1cPTIM_SMCR_ETF_2bPTIM_SMCR_ETF_3aPTIM_SMCR_ETPS_PosPTIM_SMCR_ETPS_MskPTIM_SMCR_ETPSPTIM_SMCR_ETPS_0PTIM_SMCR_ETPS_1PTIM_SMCR_ECE_PospPTIM_SMCR_ECE_MskwP TIM_SMCR_ECE PTIM_SMCR_ETP_PosTPTIM_SMCR_ETP_Msk[P TIM_SMCR_ETPPTIM_DIER_UIE_PoskPTIM_DIER_UIE_MskrP TIM_DIER_UIEPTIM_DIER_CC1IE_PosPTIM_DIER_CC1IE_Msk PTIM_DIER_CC1IEPTIM_DIER_CC2IE_PosPTIM_DIER_CC2IE_Msk PTIM_DIER_CC2IEPTIM_DIER_CC3IE_PosPTIM_DIER_CC3IE_Msk PTIM_DIER_CC3IEPTIM_DIER_CC4IE_PosPTIM_DIER_CC4IE_Msk PTIM_DIER_CC4IEPTIM_DIER_COMIE_PosPTIM_DIER_COMIE_MskPTIM_DIER_COMIEvPTIM_DIER_TIE_PoslPTIM_DIER_TIE_MsksP TIM_DIER_TIEPTIM_DIER_BIE_Pos~PTIM_DIER_BIE_MskP TIM_DIER_BIEPTIM_DIER_UDE_PospPTIM_DIER_UDE_MskwP TIM_DIER_UDE PTIM_DIER_CC1DE_Pos PTIM_DIER_CC1DE_MskPTIM_DIER_CC1DEPTIM_DIER_CC2DE_Pos PTIM_DIER_CC2DE_MskPTIM_DIER_CC2DEPTIM_DIER_CC3DE_PosPTIM_DIER_CC3DE_MskPTIM_DIER_CC3DEPTIM_DIER_CC4DE_PosPTIM_DIER_CC4DE_MskPTIM_DIER_CC4DEPTIM_DIER_COMDE_PosPTIM_DIER_COMDE_MskPTIM_DIER_COMDE{PTIM_DIER_TDE_PosqPTIM_DIER_TDE_MskxP TIM_DIER_TDE PTIM_SR_UIF_PosPTIM_SR_UIF_MskP TIM_SR_UIFPTIM_SR_CC1IF_PosPTIM_SR_CC1IF_MskP TIM_SR_CC1IF PTIM_SR_CC2IF_PosPTIM_SR_CC2IF_MskP TIM_SR_CC2IFPTIM_SR_CC3IF_PosPTIM_SR_CC3IF_MskP TIM_SR_CC3IFPTIM_SR_CC4IF_PosPTIM_SR_CC4IF_MskP TIM_SR_CC4IFPTIM_SR_COMIF_Pos_PTIM_SR_COMIF_MskfP TIM_SR_COMIFPTIM_SR_TIF_PosPTIM_SR_TIF_MskP TIM_SR_TIFPTIM_SR_BIF_PosPTIM_SR_BIF_MskP TIM_SR_BIFPTIM_SR_CC1OF_PosPTIM_SR_CC1OF_MskP TIM_SR_CC1OFPTIM_SR_CC2OF_PosPTIM_SR_CC2OF_MskP TIM_SR_CC2OFPTIM_SR_CC3OF_PosPTIM_SR_CC3OF_MskP TIM_SR_CC3OFPTIM_SR_CC4OF_Pos~PTIM_SR_CC4OF_MskP TIM_SR_CC4OFPTIM_EGR_UG_PosPTIM_EGR_UG_MskP TIM_EGR_UGPTIM_EGR_CC1G_PosPTIM_EGR_CC1G_MskP TIM_EGR_CC1G/PTIM_EGR_CC2G_PosPTIM_EGR_CC2G_MskP TIM_EGR_CC2G.PTIM_EGR_CC3G_PosPTIM_EGR_CC3G_MskP TIM_EGR_CC3G-PTIM_EGR_CC4G_PosPTIM_EGR_CC4G_MskP TIM_EGR_CC4G,PTIM_EGR_COMG_PosnPTIM_EGR_COMG_MskuP TIM_EGR_COMGPTIM_EGR_TG_PosPTIM_EGR_TG_MskP TIM_EGR_TGPTIM_EGR_BG_PosPTIM_EGR_BG_MskP TIM_EGR_BGPTIM_CCMR1_CC1S_PosPTIM_CCMR1_CC1S_MskPTIM_CCMR1_CC1SPTIM_CCMR1_CC1S_0PTIM_CCMR1_CC1S_1PTIM_CCMR1_OC1FE_PosPTIM_CCMR1_OC1FE_MskPTIM_CCMR1_OC1FEaPTIM_CCMR1_OC1PE_PosPTIM_CCMR1_OC1PE_MskPTIM_CCMR1_OC1PEWPTIM_CCMR1_OC1M_PosPTIM_CCMR1_OC1M_MskPTIM_CCMR1_OC1MPTIM_CCMR1_OC1M_0PTIM_CCMR1_OC1M_1 PTIM_CCMR1_OC1M_2 PTIM_CCMR1_OC1CE_PosPTIM_CCMR1_OC1CE_MskPTIM_CCMR1_OC1CEdPTIM_CCMR1_CC2S_Pos PTIM_CCMR1_CC2S_MskPTIM_CCMR1_CC2SPTIM_CCMR1_CC2S_0PTIM_CCMR1_CC2S_1PTIM_CCMR1_OC2FE_PosPTIM_CCMR1_OC2FE_MskPTIM_CCMR1_OC2FE`PTIM_CCMR1_OC2PE_PosPTIM_CCMR1_OC2PE_MskPTIM_CCMR1_OC2PEVPTIM_CCMR1_OC2M_PosPTIM_CCMR1_OC2M_MskPTIM_CCMR1_OC2MPTIM_CCMR1_OC2M_0 PTIM_CCMR1_OC2M_1 PTIM_CCMR1_OC2M_2 PTIM_CCMR1_OC2CE_PosPTIM_CCMR1_OC2CE_MskPTIM_CCMR1_OC2CEcPTIM_CCMR1_IC1PSC_PosqPTIM_CCMR1_IC1PSC_MskxPTIM_CCMR1_IC1PSC PTIM_CCMR1_IC1PSC_0wPTIM_CCMR1_IC1PSC_1vPTIM_CCMR1_IC1F_PosPTIM_CCMR1_IC1F_MskPTIM_CCMR1_IC1FPTIM_CCMR1_IC1F_0PTIM_CCMR1_IC1F_1PTIM_CCMR1_IC1F_2PTIM_CCMR1_IC1F_3PTIM_CCMR1_IC2PSC_PospPTIM_CCMR1_IC2PSC_MskwPTIM_CCMR1_IC2PSC PTIM_CCMR1_IC2PSC_0vPTIM_CCMR1_IC2PSC_1uPTIM_CCMR1_IC2F_PosPTIM_CCMR1_IC2F_MskPTIM_CCMR1_IC2FPTIM_CCMR1_IC2F_0PTIM_CCMR1_IC2F_1PTIM_CCMR1_IC2F_2PTIM_CCMR1_IC2F_3PTIM_CCMR2_CC3S_Pos PTIM_CCMR2_CC3S_MskPTIM_CCMR2_CC3SPTIM_CCMR2_CC3S_0PTIM_CCMR2_CC3S_1PTIM_CCMR2_OC3FE_PosPTIM_CCMR2_OC3FE_MskPTIM_CCMR2_OC3FE^PTIM_CCMR2_OC3PE_PosPTIM_CCMR2_OC3PE_MskPTIM_CCMR2_OC3PETPTIM_CCMR2_OC3M_PosPTIM_CCMR2_OC3M_Msk PTIM_CCMR2_OC3MPTIM_CCMR2_OC3M_0 PTIM_CCMR2_OC3M_1 PTIM_CCMR2_OC3M_2 PTIM_CCMR2_OC3CE_PosPTIM_CCMR2_OC3CE_MskPTIM_CCMR2_OC3CEaPTIM_CCMR2_CC4S_Pos PTIM_CCMR2_CC4S_MskPTIM_CCMR2_CC4SPTIM_CCMR2_CC4S_0PTIM_CCMR2_CC4S_1PTIM_CCMR2_OC4FE_PosPTIM_CCMR2_OC4FE_MskPTIM_CCMR2_OC4FE]PTIM_CCMR2_OC4PE_PosPTIM_CCMR2_OC4PE_MskPTIM_CCMR2_OC4PESPTIM_CCMR2_OC4M_PosPTIM_CCMR2_OC4M_Msk PTIM_CCMR2_OC4MPTIM_CCMR2_OC4M_0 PTIM_CCMR2_OC4M_1 PTIM_CCMR2_OC4M_2PTIM_CCMR2_OC4CE_PosPTIM_CCMR2_OC4CE_MskPTIM_CCMR2_OC4CE`PTIM_CCMR2_IC3PSC_PosnPTIM_CCMR2_IC3PSC_MskuPTIM_CCMR2_IC3PSCPTIM_CCMR2_IC3PSC_0tPTIM_CCMR2_IC3PSC_1sPTIM_CCMR2_IC3F_PosPTIM_CCMR2_IC3F_MskPTIM_CCMR2_IC3FPTIM_CCMR2_IC3F_0PTIM_CCMR2_IC3F_1PTIM_CCMR2_IC3F_2PTIM_CCMR2_IC3F_3PTIM_CCMR2_IC4PSC_PosmPTIM_CCMR2_IC4PSC_MsktPTIM_CCMR2_IC4PSCPTIM_CCMR2_IC4PSC_0sPTIM_CCMR2_IC4PSC_1rPTIM_CCMR2_IC4F_PosPTIM_CCMR2_IC4F_MskPTIM_CCMR2_IC4FPTIM_CCMR2_IC4F_0PTIM_CCMR2_IC4F_1PTIM_CCMR2_IC4F_2PTIM_CCMR2_IC4F_3PTIM_CCER_CC1E_PosWPTIM_CCER_CC1E_Msk^PTIM_CCER_CC1EPTIM_CCER_CC1P_PosLPTIM_CCER_CC1P_MskSPTIM_CCER_CC1PPTIM_CCER_CC1NE_PosPTIM_CCER_CC1NE_MskPTIM_CCER_CC1NEPTIM_CCER_CC1NP_PosPTIM_CCER_CC1NP_MskPTIM_CCER_CC1NPPTIM_CCER_CC2E_PosVPTIM_CCER_CC2E_Msk]PTIM_CCER_CC2EPTIM_CCER_CC2P_PosKPTIM_CCER_CC2P_MskRPTIM_CCER_CC2PPTIM_CCER_CC2NE_PosPTIM_CCER_CC2NE_Msk PTIM_CCER_CC2NEPTIM_CCER_CC2NP_PosPTIM_CCER_CC2NP_MskPTIM_CCER_CC2NPPTIM_CCER_CC3E_PosUPTIM_CCER_CC3E_Msk\PTIM_CCER_CC3EPTIM_CCER_CC3P_PosJPTIM_CCER_CC3P_MskQPTIM_CCER_CC3PPTIM_CCER_CC3NE_PosPTIM_CCER_CC3NE_Msk PTIM_CCER_CC3NEPTIM_CCER_CC3NP_PosPTIM_CCER_CC3NP_MskPTIM_CCER_CC3NPPTIM_CCER_CC4E_PosTPTIM_CCER_CC4E_Msk[PTIM_CCER_CC4EPTIM_CCER_CC4P_PosIPTIM_CCER_CC4P_MskPPTIM_CCER_CC4PPTIM_CNT_CNT_PosPTIM_CNT_CNT_MskP TIM_CNT_CNTCPTIM_PSC_PSC_PosPTIM_PSC_PSC_MskP TIM_PSC_PSCAPTIM_ARR_ARR_PosPTIM_ARR_ARR_MskP TIM_ARR_ARRCPTIM_RCR_REP_PosPTIM_RCR_REP_MskP TIM_RCR_REP?PTIM_CCR1_CCR1_Pos^PTIM_CCR1_CCR1_MskePTIM_CCR1_CCR1PTIM_CCR2_CCR2_Pos\PTIM_CCR2_CCR2_MskcPTIM_CCR2_CCR2PTIM_CCR3_CCR3_PosZPTIM_CCR3_CCR3_MskaPTIM_CCR3_CCR3PTIM_CCR4_CCR4_PosXPTIM_CCR4_CCR4_Msk_PTIM_CCR4_CCR4PTIM_BDTR_DTG_PosgPTIM_BDTR_DTG_MsknP TIM_BDTR_DTGPTIM_BDTR_DTG_0mPTIM_BDTR_DTG_1lPTIM_BDTR_DTG_2kPTIM_BDTR_DTG_3jPTIM_BDTR_DTG_4iPTIM_BDTR_DTG_5hPTIM_BDTR_DTG_6gPTIM_BDTR_DTG_7fPTIM_BDTR_LOCK_PosPTIM_BDTR_LOCK_Msk"PTIM_BDTR_LOCKPTIM_BDTR_LOCK_0!PTIM_BDTR_LOCK_1 PTIM_BDTR_OSSI_PosPTIM_BDTR_OSSI_Msk PTIM_BDTR_OSSIPTIM_BDTR_OSSR_PosPTIM_BDTR_OSSR_MskPTIM_BDTR_OSSRPTIM_BDTR_BKE_PostPTIM_BDTR_BKE_Msk{P TIM_BDTR_BKE PTIM_BDTR_BKP_PosiPTIM_BDTR_BKP_MskpP TIM_BDTR_BKPPTIM_BDTR_AOE_PosqPTIM_BDTR_AOE_MskxP TIM_BDTR_AOE PTIM_BDTR_MOE_PosePTIM_BDTR_MOE_MsklP TIM_BDTR_MOEPTIM_DCR_DBA_PosPTIM_DCR_DBA_MskP TIM_DCR_DBAmPTIM_DCR_DBA_0PTIM_DCR_DBA_1PTIM_DCR_DBA_2PTIM_DCR_DBA_3PTIM_DCR_DBA_4PTIM_DCR_DBL_PosPTIM_DCR_DBL_MskP TIM_DCR_DBLbPTIM_DCR_DBL_0PTIM_DCR_DBL_1PTIM_DCR_DBL_2PTIM_DCR_DBL_3PTIM_DCR_DBL_4PTIM_DMAR_DMAB_Pos8PTIM_DMAR_DMAB_Msk?PTIM_DMAR_DMABPRTC_CRH_SECIE_Pos+PRTC_CRH_SECIE_Msk2PRTC_CRH_SECIEPRTC_CRH_ALRIE_Pos'PRTC_CRH_ALRIE_Msk.PRTC_CRH_ALRIEPRTC_CRH_OWIE_PosbPRTC_CRH_OWIE_MskiP RTC_CRH_OWIEPRTC_CRL_SECF_PosqPRTC_CRL_SECF_MskxP RTC_CRL_SECF PRTC_CRL_ALRF_PosmPRTC_CRL_ALRF_MsktP RTC_CRL_ALRFPRTC_CRL_OWF_PosPRTC_CRL_OWF_MskP RTC_CRL_OWFAPRTC_CRL_RSF_PosPRTC_CRL_RSF_MskP RTC_CRL_RSFBPRTC_CRL_CNF_PosPRTC_CRL_CNF_MskP RTC_CRL_CNFVPRTC_CRL_RTOFF_PosPRTC_CRL_RTOFF_MskPRTC_CRL_RTOFFPRTC_PRLH_PRL_PosOPRTC_PRLH_PRL_MskVP RTC_PRLH_PRLPRTC_PRLL_PRL_PosKPRTC_PRLL_PRL_MskRP RTC_PRLL_PRLPRTC_DIVH_RTC_DIV_PosPRTC_DIVH_RTC_DIV_MskPRTC_DIVH_RTC_DIVPRTC_DIVL_RTC_DIV_PosPRTC_DIVL_RTC_DIV_MskPRTC_DIVL_RTC_DIVPRTC_CNTH_RTC_CNT_PosPRTC_CNTH_RTC_CNT_MskPRTC_CNTH_RTC_CNTPRTC_CNTL_RTC_CNT_Pos PRTC_CNTL_RTC_CNT_MskPRTC_CNTL_RTC_CNTPRTC_ALRH_RTC_ALR_PosPRTC_ALRH_RTC_ALR_Msk$PRTC_ALRH_RTC_ALRPRTC_ALRL_RTC_ALR_PosPRTC_ALRL_RTC_ALR_Msk PRTC_ALRL_RTC_ALRPIWDG_KR_KEY_PosPIWDG_KR_KEY_MskP IWDG_KR_KEYFPIWDG_PR_PR_PosPIWDG_PR_PR_MskP IWDG_PR_PRP IWDG_PR_PR_0P IWDG_PR_PR_1P IWDG_PR_PR_2PIWDG_RLR_RL_PosPIWDG_RLR_RL_MskP IWDG_RLR_RL>PIWDG_SR_PVU_PosPIWDG_SR_PVU_MskP IWDG_SR_PVU,PIWDG_SR_RVU_PosPIWDG_SR_RVU_MskP IWDG_SR_RVU*PWWDG_CR_T_Pos@PWWDG_CR_T_MskGP WWDG_CR_TP WWDG_CR_T_0FP WWDG_CR_T_1EP WWDG_CR_T_2DP WWDG_CR_T_3CP WWDG_CR_T_4BP WWDG_CR_T_5AP WWDG_CR_T_6@P WWDG_CR_T0P WWDG_CR_T1P WWDG_CR_T2P WWDG_CR_T3P WWDG_CR_T4P WWDG_CR_T5P WWDG_CR_T6PWWDG_CR_WDGA_PoskPWWDG_CR_WDGA_MskrP WWDG_CR_WDGAPWWDG_CFR_W_PosPWWDG_CFR_W_MskP WWDG_CFR_WP WWDG_CFR_W_0P WWDG_CFR_W_1P WWDG_CFR_W_2P WWDG_CFR_W_3P WWDG_CFR_W_4P WWDG_CFR_W_5P WWDG_CFR_W_6P WWDG_CFR_W0\P WWDG_CFR_W1[P WWDG_CFR_W2ZP WWDG_CFR_W3YP WWDG_CFR_W4XP WWDG_CFR_W5WP WWDG_CFR_W6VPWWDG_CFR_WDGTB_PosPWWDG_CFR_WDGTB_MskPWWDG_CFR_WDGTBePWWDG_CFR_WDGTB_0PWWDG_CFR_WDGTB_1PWWDG_CFR_WDGTB03PWWDG_CFR_WDGTB12PWWDG_CFR_EWI_PoscPWWDG_CFR_EWI_MskjP WWDG_CFR_EWIPWWDG_SR_EWIF_PosSPWWDG_SR_EWIF_MskZP WWDG_SR_EWIFPFSMC_BCRx_MBKEN_PosqPFSMC_BCRx_MBKEN_MskxPFSMC_BCRx_MBKEN PFSMC_BCRx_MUXEN_PosQPFSMC_BCRx_MUXEN_MskXPFSMC_BCRx_MUXENPFSMC_BCRx_MTYP_PosPFSMC_BCRx_MTYP_MskPFSMC_BCRx_MTYP/PFSMC_BCRx_MTYP_0PFSMC_BCRx_MTYP_1PFSMC_BCRx_MWID_PosPFSMC_BCRx_MWID_MskPFSMC_BCRx_MWIDHPFSMC_BCRx_MWID_0PFSMC_BCRx_MWID_1PFSMC_BCRx_FACCEN_Pos<PFSMC_BCRx_FACCEN_MskCPFSMC_BCRx_FACCENPFSMC_BCRx_BURSTEN_PosPFSMC_BCRx_BURSTEN_MskPFSMC_BCRx_BURSTENPPFSMC_BCRx_WAITPOL_PosPFSMC_BCRx_WAITPOL_MskPFSMC_BCRx_WAITPOLSPFSMC_BCRx_WRAPMOD_PosPFSMC_BCRx_WRAPMOD_MskPFSMC_BCRx_WRAPMODYPFSMC_BCRx_WAITCFG_PosPFSMC_BCRx_WAITCFG_MskPFSMC_BCRx_WAITCFGnPFSMC_BCRx_WREN_PosPFSMC_BCRx_WREN_MskPFSMC_BCRx_WREN=PFSMC_BCRx_WAITEN_PosPFSMC_BCRx_WAITEN_MskPFSMC_BCRx_WAITENPFSMC_BCRx_EXTMOD_Pos PFSMC_BCRx_EXTMOD_MskPFSMC_BCRx_EXTMOD PFSMC_BCRx_ASYNCWAIT_Pos# PFSMC_BCRx_ASYNCWAIT_Msk*PFSMC_BCRx_ASYNCWAITPFSMC_BCRx_CBURSTRW_Pos\PFSMC_BCRx_CBURSTRW_MskcPFSMC_BCRx_CBURSTRWPFSMC_BTRx_ADDSET_PosPFSMC_BTRx_ADDSET_MskPFSMC_BTRx_ADDSETPFSMC_BTRx_ADDSET_0PFSMC_BTRx_ADDSET_1PFSMC_BTRx_ADDSET_2PFSMC_BTRx_ADDSET_3PFSMC_BTRx_ADDHLD_Pos*PFSMC_BTRx_ADDHLD_Msk1PFSMC_BTRx_ADDHLDPFSMC_BTRx_ADDHLD_00PFSMC_BTRx_ADDHLD_1/PFSMC_BTRx_ADDHLD_2.PFSMC_BTRx_ADDHLD_3-PFSMC_BTRx_DATAST_Pos PFSMC_BTRx_DATAST_MskPFSMC_BTRx_DATASTPFSMC_BTRx_DATAST_0PFSMC_BTRx_DATAST_1PFSMC_BTRx_DATAST_2PFSMC_BTRx_DATAST_3 PFSMC_BTRx_DATAST_4 PFSMC_BTRx_DATAST_5 PFSMC_BTRx_DATAST_6 PFSMC_BTRx_DATAST_7 PFSMC_BTRx_BUSTURN_PosPFSMC_BTRx_BUSTURN_MskPFSMC_BTRx_BUSTURN/PFSMC_BTRx_BUSTURN_0PFSMC_BTRx_BUSTURN_1PFSMC_BTRx_BUSTURN_2PFSMC_BTRx_BUSTURN_3PFSMC_BTRx_CLKDIV_PosPFSMC_BTRx_CLKDIV_MskPFSMC_BTRx_CLKDIVPFSMC_BTRx_CLKDIV_0PFSMC_BTRx_CLKDIV_1PFSMC_BTRx_CLKDIV_2PFSMC_BTRx_CLKDIV_3PFSMC_BTRx_DATLAT_PosPFSMC_BTRx_DATLAT_MskPFSMC_BTRx_DATLATPFSMC_BTRx_DATLAT_0PFSMC_BTRx_DATLAT_1PFSMC_BTRx_DATLAT_2PFSMC_BTRx_DATLAT_3PFSMC_BTRx_ACCMOD_Pos$PFSMC_BTRx_ACCMOD_Msk+PFSMC_BTRx_ACCMODPFSMC_BTRx_ACCMOD_0*PFSMC_BTRx_ACCMOD_1)PFSMC_BWTRx_ADDSET_PosPFSMC_BWTRx_ADDSET_MskPFSMC_BWTRx_ADDSETVPFSMC_BWTRx_ADDSET_0PFSMC_BWTRx_ADDSET_1PFSMC_BWTRx_ADDSET_2PFSMC_BWTRx_ADDSET_3PFSMC_BWTRx_ADDHLD_PosPFSMC_BWTRx_ADDHLD_MskPFSMC_BWTRx_ADDHLDjPFSMC_BWTRx_ADDHLD_0PFSMC_BWTRx_ADDHLD_1PFSMC_BWTRx_ADDHLD_2PFSMC_BWTRx_ADDHLD_3PFSMC_BWTRx_DATAST_PosPFSMC_BWTRx_DATAST_MskPFSMC_BWTRx_DATASTJPFSMC_BWTRx_DATAST_0PFSMC_BWTRx_DATAST_1PFSMC_BWTRx_DATAST_2PFSMC_BWTRx_DATAST_3PFSMC_BWTRx_DATAST_4PFSMC_BWTRx_DATAST_5PFSMC_BWTRx_DATAST_6PFSMC_BWTRx_DATAST_7PFSMC_BWTRx_BUSTURN_Pos=PFSMC_BWTRx_BUSTURN_MskDPFSMC_BWTRx_BUSTURNPFSMC_BWTRx_BUSTURN_0CPFSMC_BWTRx_BUSTURN_1BPFSMC_BWTRx_BUSTURN_2APFSMC_BWTRx_BUSTURN_3@PFSMC_BWTRx_ACCMOD_PosPFSMC_BWTRx_ACCMOD_MskPFSMC_BWTRx_ACCMODdPFSMC_BWTRx_ACCMOD_0PFSMC_BWTRx_ACCMOD_1PFSMC_PCRx_PWAITEN_PosPFSMC_PCRx_PWAITEN_MskPFSMC_PCRx_PWAITENMPFSMC_PCRx_PBKEN_Pos`PFSMC_PCRx_PBKEN_MskgPFSMC_PCRx_PBKENPFSMC_PCRx_PTYP_PosPFSMC_PCRx_PTYP_MskPFSMC_PCRx_PTYPPFSMC_PCRx_PWID_PosPFSMC_PCRx_PWID_MskPFSMC_PCRx_PWID7PFSMC_PCRx_PWID_0PFSMC_PCRx_PWID_1PFSMC_PCRx_ECCEN_PosrPFSMC_PCRx_ECCEN_MskyPFSMC_PCRx_ECCEN PFSMC_PCRx_TCLR_PosPFSMC_PCRx_TCLR_MskPFSMC_PCRx_TCLR6PFSMC_PCRx_TCLR_0PFSMC_PCRx_TCLR_1PFSMC_PCRx_TCLR_2PFSMC_PCRx_TCLR_3PFSMC_PCRx_TAR_PosPFSMC_PCRx_TAR_MskPFSMC_PCRx_TARPFSMC_PCRx_TAR_0PFSMC_PCRx_TAR_1PFSMC_PCRx_TAR_2PFSMC_PCRx_TAR_3PFSMC_PCRx_ECCPS_PosbPFSMC_PCRx_ECCPS_MskiPFSMC_PCRx_ECCPSPFSMC_PCRx_ECCPS_0hPFSMC_PCRx_ECCPS_1gPFSMC_PCRx_ECCPS_2fPFSMC_SRx_IRS_Pos(PFSMC_SRx_IRS_Msk/P FSMC_SRx_IRSPFSMC_SRx_ILS_Pos.PFSMC_SRx_ILS_Msk5P FSMC_SRx_ILSPFSMC_SRx_IFS_Pos4PFSMC_SRx_IFS_Msk;P FSMC_SRx_IFSPFSMC_SRx_IREN_PosPFSMC_SRx_IREN_MskPFSMC_SRx_IRENPFSMC_SRx_ILEN_PosPFSMC_SRx_ILEN_MskPFSMC_SRx_ILENPFSMC_SRx_IFEN_PosPFSMC_SRx_IFEN_MskPFSMC_SRx_IFENPFSMC_SRx_FEMPT_PosPFSMC_SRx_FEMPT_MskPFSMC_SRx_FEMPT/PFSMC_PMEMx_MEMSETx_Pos=PFSMC_PMEMx_MEMSETx_MskDPFSMC_PMEMx_MEMSETxPFSMC_PMEMx_MEMSETx_0CPFSMC_PMEMx_MEMSETx_1BPFSMC_PMEMx_MEMSETx_2APFSMC_PMEMx_MEMSETx_3@PFSMC_PMEMx_MEMSETx_4?PFSMC_PMEMx_MEMSETx_5>PFSMC_PMEMx_MEMSETx_6=PFSMC_PMEMx_MEMSETx_7< PFSMC_PMEMx_MEMWAITx_Pos PFSMC_PMEMx_MEMWAITx_MskPFSMC_PMEMx_MEMWAITxPFSMC_PMEMx_MEMWAIT2_0>PFSMC_PMEMx_MEMWAITx_1PFSMC_PMEMx_MEMWAITx_2PFSMC_PMEMx_MEMWAITx_3PFSMC_PMEMx_MEMWAITx_4PFSMC_PMEMx_MEMWAITx_5PFSMC_PMEMx_MEMWAITx_6PFSMC_PMEMx_MEMWAITx_7 PFSMC_PMEMx_MEMHOLDx_Pos PFSMC_PMEMx_MEMHOLDx_MskPFSMC_PMEMx_MEMHOLDxPFSMC_PMEMx_MEMHOLDx_0PFSMC_PMEMx_MEMHOLDx_1PFSMC_PMEMx_MEMHOLDx_2PFSMC_PMEMx_MEMHOLDx_3PFSMC_PMEMx_MEMHOLDx_4PFSMC_PMEMx_MEMHOLDx_5PFSMC_PMEMx_MEMHOLDx_6PFSMC_PMEMx_MEMHOLDx_7PFSMC_PMEMx_MEMHIZx_Pos>PFSMC_PMEMx_MEMHIZx_MskEPFSMC_PMEMx_MEMHIZxPFSMC_PMEMx_MEMHIZx_0DPFSMC_PMEMx_MEMHIZx_1CPFSMC_PMEMx_MEMHIZx_2BPFSMC_PMEMx_MEMHIZx_3APFSMC_PMEMx_MEMHIZx_4@PFSMC_PMEMx_MEMHIZx_5?PFSMC_PMEMx_MEMHIZx_6>PFSMC_PMEMx_MEMHIZx_7=PFSMC_PATTx_ATTSETx_Pos)PFSMC_PATTx_ATTSETx_Msk0PFSMC_PATTx_ATTSETxPFSMC_PATTx_ATTSETx_0/PFSMC_PATTx_ATTSETx_1.PFSMC_PATTx_ATTSETx_2-PFSMC_PATTx_ATTSETx_3,PFSMC_PATTx_ATTSETx_4+PFSMC_PATTx_ATTSETx_5*PFSMC_PATTx_ATTSETx_6)PFSMC_PATTx_ATTSETx_7( PFSMC_PATTx_ATTWAITx_Pos PFSMC_PATTx_ATTWAITx_MskPFSMC_PATTx_ATTWAITxwPFSMC_PATTx_ATTWAITx_0PFSMC_PATTx_ATTWAITx_1PFSMC_PATTx_ATTWAITx_2PFSMC_PATTx_ATTWAITx_3PFSMC_PATTx_ATTWAITx_4PFSMC_PATTx_ATTWAITx_5PFSMC_PATTx_ATTWAITx_6PFSMC_PATTx_ATTWAITx_7 PFSMC_PATTx_ATTHOLDx_Pos PFSMC_PATTx_ATTHOLDx_MskPFSMC_PATTx_ATTHOLDxPFSMC_PATTx_ATTHOLDx_0PFSMC_PATTx_ATTHOLDx_1PFSMC_PATTx_ATTHOLDx_2PFSMC_PATTx_ATTHOLDx_3PFSMC_PATTx_ATTHOLDx_4PFSMC_PATTx_ATTHOLDx_5PFSMC_PATTx_ATTHOLDx_6PFSMC_PATTx_ATTHOLDx_7PFSMC_PATTx_ATTHIZx_Pos*PFSMC_PATTx_ATTHIZx_Msk1PFSMC_PATTx_ATTHIZxPFSMC_PATTx_ATTHIZx_00PFSMC_PATTx_ATTHIZx_1/PFSMC_PATTx_ATTHIZx_2.PFSMC_PATTx_ATTHIZx_3-PFSMC_PATTx_ATTHIZx_4,PFSMC_PATTx_ATTHIZx_5+PFSMC_PATTx_ATTHIZx_6*PFSMC_PATTx_ATTHIZx_7)PFSMC_PIO4_IOSET4_PosWPFSMC_PIO4_IOSET4_Msk^PFSMC_PIO4_IOSET4PFSMC_PIO4_IOSET4_0]PFSMC_PIO4_IOSET4_1\PFSMC_PIO4_IOSET4_2[PFSMC_PIO4_IOSET4_3ZPFSMC_PIO4_IOSET4_4YPFSMC_PIO4_IOSET4_5XPFSMC_PIO4_IOSET4_6WPFSMC_PIO4_IOSET4_7VPFSMC_PIO4_IOWAIT4_Pos PFSMC_PIO4_IOWAIT4_MskPFSMC_PIO4_IOWAIT4PFSMC_PIO4_IOWAIT4_0PFSMC_PIO4_IOWAIT4_1PFSMC_PIO4_IOWAIT4_2PFSMC_PIO4_IOWAIT4_3PFSMC_PIO4_IOWAIT4_4PFSMC_PIO4_IOWAIT4_5 PFSMC_PIO4_IOWAIT4_6 PFSMC_PIO4_IOWAIT4_7 PFSMC_PIO4_IOHOLD4_PosPFSMC_PIO4_IOHOLD4_Msk!PFSMC_PIO4_IOHOLD4PFSMC_PIO4_IOHOLD4_0 PFSMC_PIO4_IOHOLD4_1PFSMC_PIO4_IOHOLD4_2PFSMC_PIO4_IOHOLD4_3PFSMC_PIO4_IOHOLD4_4PFSMC_PIO4_IOHOLD4_5PFSMC_PIO4_IOHOLD4_6PFSMC_PIO4_IOHOLD4_7PFSMC_PIO4_IOHIZ4_PosXPFSMC_PIO4_IOHIZ4_Msk_PFSMC_PIO4_IOHIZ4PFSMC_PIO4_IOHIZ4_0^PFSMC_PIO4_IOHIZ4_1]PFSMC_PIO4_IOHIZ4_2\PFSMC_PIO4_IOHIZ4_3[PFSMC_PIO4_IOHIZ4_4ZPFSMC_PIO4_IOHIZ4_5YPFSMC_PIO4_IOHIZ4_6XPFSMC_PIO4_IOHIZ4_7WPFSMC_ECCR2_ECC2_PosPFSMC_ECCR2_ECC2_MskPFSMC_ECCR2_ECC2zPFSMC_ECCR3_ECC3_PosPFSMC_ECCR3_ECC3_MskPFSMC_ECCR3_ECC3xPSDIO_POWER_PWRCTRL_PosfPSDIO_POWER_PWRCTRL_MskmPSDIO_POWER_PWRCTRLPSDIO_POWER_PWRCTRL_0lPSDIO_POWER_PWRCTRL_1kPSDIO_CLKCR_CLKDIV_PosPSDIO_CLKCR_CLKDIV_MskPSDIO_CLKCR_CLKDIVPSDIO_CLKCR_CLKEN_PosIPSDIO_CLKCR_CLKEN_MskPPSDIO_CLKCR_CLKENPSDIO_CLKCR_PWRSAV_PosPSDIO_CLKCR_PWRSAV_MskPSDIO_CLKCR_PWRSAVjPSDIO_CLKCR_BYPASS_PosPSDIO_CLKCR_BYPASS_MskPSDIO_CLKCR_BYPASS{PSDIO_CLKCR_WIDBUS_PosPSDIO_CLKCR_WIDBUS_MskPSDIO_CLKCR_WIDBUSPSDIO_CLKCR_WIDBUS_0PSDIO_CLKCR_WIDBUS_1PSDIO_CLKCR_NEGEDGE_PosPSDIO_CLKCR_NEGEDGE_MskPSDIO_CLKCR_NEGEDGE\PSDIO_CLKCR_HWFC_EN_PosPSDIO_CLKCR_HWFC_EN_MskPSDIO_CLKCR_HWFC_EN1PSDIO_ARG_CMDARG_PosPSDIO_ARG_CMDARG_MskPSDIO_ARG_CMDARG8PSDIO_CMD_CMDINDEX_PosPSDIO_CMD_CMDINDEX_Msk PSDIO_CMD_CMDINDEXPSDIO_CMD_WAITRESP_PosPSDIO_CMD_WAITRESP_MskPSDIO_CMD_WAITRESPyPSDIO_CMD_WAITRESP_0PSDIO_CMD_WAITRESP_1PSDIO_CMD_WAITINT_Pos1PSDIO_CMD_WAITINT_Msk8PSDIO_CMD_WAITINTPSDIO_CMD_WAITPEND_PosPSDIO_CMD_WAITPEND_MskPSDIO_CMD_WAITPENDPSDIO_CMD_CPSMEN_PosPSDIO_CMD_CPSMEN_MskPSDIO_CMD_CPSMEN&!PSDIO_CMD_SDIOSUSPEND_Pos!PSDIO_CMD_SDIOSUSPEND_MskPSDIO_CMD_SDIOSUSPEND PSDIO_CMD_ENCMDCOMPL_Posi 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PSDIO_DCTRL_DBLOCKSIZE_0 PSDIO_DCTRL_DBLOCKSIZE_1 PSDIO_DCTRL_DBLOCKSIZE_2 PSDIO_DCTRL_DBLOCKSIZE_3PSDIO_DCTRL_RWSTART_PosqPSDIO_DCTRL_RWSTART_MskxPSDIO_DCTRL_RWSTART PSDIO_DCTRL_RWSTOP_PosPSDIO_DCTRL_RWSTOP_MskPSDIO_DCTRL_RWSTOPTPSDIO_DCTRL_RWMOD_Pos#PSDIO_DCTRL_RWMOD_Msk*PSDIO_DCTRL_RWMODPSDIO_DCTRL_SDIOEN_PosPSDIO_DCTRL_SDIOEN_MskPSDIO_DCTRL_SDIOEN"PSDIO_DCOUNT_DATACOUNT_Pos"PSDIO_DCOUNT_DATACOUNT_MskPSDIO_DCOUNT_DATACOUNTDPSDIO_STA_CCRCFAIL_PosPSDIO_STA_CCRCFAIL_Msk PSDIO_STA_CCRCFAILPSDIO_STA_DCRCFAIL_PosPSDIO_STA_DCRCFAIL_Msk PSDIO_STA_DCRCFAILPSDIO_STA_CTIMEOUT_PosPSDIO_STA_CTIMEOUT_MskPSDIO_STA_CTIMEOUTjPSDIO_STA_DTIMEOUT_PosPSDIO_STA_DTIMEOUT_MskPSDIO_STA_DTIMEOUTiPSDIO_STA_TXUNDERR_PosPSDIO_STA_TXUNDERR_MskPSDIO_STA_TXUNDERRXPSDIO_STA_RXOVERR_PosPSDIO_STA_RXOVERR_Msk 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CAN_TSR_LOW:PCAN_TSR_LOW0_PosoPCAN_TSR_LOW0_MskvP CAN_TSR_LOW0PCAN_TSR_LOW1_PosnPCAN_TSR_LOW1_MskuP CAN_TSR_LOW1PCAN_TSR_LOW2_PosmPCAN_TSR_LOW2_MsktP CAN_TSR_LOW2PCAN_RF0R_FMP0_Pos[PCAN_RF0R_FMP0_MskbPCAN_RF0R_FMP0PCAN_RF0R_FULL0_Pos PCAN_RF0R_FULL0_MskPCAN_RF0R_FULL0PCAN_RF0R_FOVR0_PosPCAN_RF0R_FOVR0_MskPCAN_RF0R_FOVR0PCAN_RF0R_RFOM0_PosPCAN_RF0R_RFOM0_MskPCAN_RF0R_RFOM0PCAN_RF1R_FMP1_PosYPCAN_RF1R_FMP1_Msk`PCAN_RF1R_FMP1PCAN_RF1R_FULL1_PosPCAN_RF1R_FULL1_MskPCAN_RF1R_FULL1PCAN_RF1R_FOVR1_PosPCAN_RF1R_FOVR1_MskPCAN_RF1R_FOVR1PCAN_RF1R_RFOM1_PosPCAN_RF1R_RFOM1_Msk PCAN_RF1R_RFOM1PCAN_IER_TMEIE_Pos4PCAN_IER_TMEIE_Msk;PCAN_IER_TMEIEPCAN_IER_FMPIE0_PosPCAN_IER_FMPIE0_Msk PCAN_IER_FMPIE0PCAN_IER_FFIE0_Pos^PCAN_IER_FFIE0_MskePCAN_IER_FFIE0PCAN_IER_FOVIE0_PosPCAN_IER_FOVIE0_MskPCAN_IER_FOVIE0PCAN_IER_FMPIE1_PosPCAN_IER_FMPIE1_Msk PCAN_IER_FMPIE1PCAN_IER_FFIE1_Pos]PCAN_IER_FFIE1_MskdPCAN_IER_FFIE1PCAN_IER_FOVIE1_PosPCAN_IER_FOVIE1_MskPCAN_IER_FOVIE1PCAN_IER_EWGIE_Pos7PCAN_IER_EWGIE_Msk>PCAN_IER_EWGIEPCAN_IER_EPVIE_Pos/PCAN_IER_EPVIE_Msk6PCAN_IER_EPVIEPCAN_IER_BOFIE_PosCPCAN_IER_BOFIE_MskJPCAN_IER_BOFIEPCAN_IER_LECIE_PosFPCAN_IER_LECIE_MskMPCAN_IER_LECIEPCAN_IER_ERRIE_Pos1PCAN_IER_ERRIE_Msk8PCAN_IER_ERRIEPCAN_IER_WKUIE_Pos#PCAN_IER_WKUIE_Msk*PCAN_IER_WKUIEPCAN_IER_SLKIE_Pos0PCAN_IER_SLKIE_Msk7PCAN_IER_SLKIEPCAN_ESR_EWGF_PoswPCAN_ESR_EWGF_Msk~P CAN_ESR_EWGFPCAN_ESR_EPVF_PosoPCAN_ESR_EPVF_MskvP CAN_ESR_EPVFPCAN_ESR_BOFF_PosPCAN_ESR_BOFF_MskP CAN_ESR_BOFFPCAN_ESR_LEC_PosPCAN_ESR_LEC_MskP CAN_ESR_LECgPCAN_ESR_LEC_0PCAN_ESR_LEC_1PCAN_ESR_LEC_2PCAN_ESR_TEC_PosPCAN_ESR_TEC_MskP CAN_ESR_TEC_PCAN_ESR_REC_PosPCAN_ESR_REC_MskP CAN_ESR_RECaPCAN_BTR_BRP_PosPCAN_BTR_BRP_MskP CAN_BTR_BRPYPCAN_BTR_TS1_PosPCAN_BTR_TS1_MskP CAN_BTR_TS1ePCAN_BTR_TS1_0PCAN_BTR_TS1_1PCAN_BTR_TS1_2PCAN_BTR_TS1_3PCAN_BTR_TS2_PosPCAN_BTR_TS2_MskP CAN_BTR_TS2dPCAN_BTR_TS2_0PCAN_BTR_TS2_1PCAN_BTR_TS2_2PCAN_BTR_SJW_PosPCAN_BTR_SJW_MskP CAN_BTR_SJWIPCAN_BTR_SJW_0PCAN_BTR_SJW_1PCAN_BTR_LBKM_Pos|PCAN_BTR_LBKM_MskP CAN_BTR_LBKMPCAN_BTR_SILM_PosmPCAN_BTR_SILM_MsktP CAN_BTR_SILMPCAN_TI0R_TXRQ_PosPCAN_TI0R_TXRQ_Msk!PCAN_TI0R_TXRQPCAN_TI0R_RTR_PossPCAN_TI0R_RTR_MskzP CAN_TI0R_RTR PCAN_TI0R_IDE_PosPCAN_TI0R_IDE_MskP CAN_TI0R_IDE2PCAN_TI0R_EXID_Pos?PCAN_TI0R_EXID_MskFPCAN_TI0R_EXIDPCAN_TI0R_STID_Pos5PCAN_TI0R_STID_Msk<PCAN_TI0R_STIDPCAN_TDT0R_DLC_PosGPCAN_TDT0R_DLC_MskNPCAN_TDT0R_DLCPCAN_TDT0R_TGT_Pos+PCAN_TDT0R_TGT_Msk2PCAN_TDT0R_TGTPCAN_TDT0R_TIME_PosPCAN_TDT0R_TIME_MskPCAN_TDT0R_TIMEPCAN_TDL0R_DATA0_PosPCAN_TDL0R_DATA0_MskPCAN_TDL0R_DATA0mPCAN_TDL0R_DATA1_PosPCAN_TDL0R_DATA1_MskPCAN_TDL0R_DATA1lPCAN_TDL0R_DATA2_PosPCAN_TDL0R_DATA2_MskPCAN_TDL0R_DATA2kPCAN_TDL0R_DATA3_PosPCAN_TDL0R_DATA3_MskPCAN_TDL0R_DATA3jPCAN_TDH0R_DATA4_PosPCAN_TDH0R_DATA4_MskPCAN_TDH0R_DATA4mPCAN_TDH0R_DATA5_PosPCAN_TDH0R_DATA5_MskPCAN_TDH0R_DATA5lPCAN_TDH0R_DATA6_PosPCAN_TDH0R_DATA6_MskPCAN_TDH0R_DATA6kPCAN_TDH0R_DATA7_PosPCAN_TDH0R_DATA7_MskPCAN_TDH0R_DATA7jPCAN_TI1R_TXRQ_PosPCAN_TI1R_TXRQ_Msk PCAN_TI1R_TXRQPCAN_TI1R_RTR_PosrPCAN_TI1R_RTR_MskyP CAN_TI1R_RTR PCAN_TI1R_IDE_PosPCAN_TI1R_IDE_MskP CAN_TI1R_IDE1PCAN_TI1R_EXID_Pos>PCAN_TI1R_EXID_MskEPCAN_TI1R_EXIDPCAN_TI1R_STID_Pos4PCAN_TI1R_STID_Msk;PCAN_TI1R_STIDPCAN_TDT1R_DLC_PosFPCAN_TDT1R_DLC_MskMPCAN_TDT1R_DLCPCAN_TDT1R_TGT_Pos*PCAN_TDT1R_TGT_Msk1PCAN_TDT1R_TGTPCAN_TDT1R_TIME_PosPCAN_TDT1R_TIME_MskPCAN_TDT1R_TIMEPCAN_TDL1R_DATA0_PosPCAN_TDL1R_DATA0_MskPCAN_TDL1R_DATA0lPCAN_TDL1R_DATA1_PosPCAN_TDL1R_DATA1_MskPCAN_TDL1R_DATA1kPCAN_TDL1R_DATA2_PosPCAN_TDL1R_DATA2_MskPCAN_TDL1R_DATA2jPCAN_TDL1R_DATA3_PosPCAN_TDL1R_DATA3_MskPCAN_TDL1R_DATA3iPCAN_TDH1R_DATA4_PosPCAN_TDH1R_DATA4_MskPCAN_TDH1R_DATA4lPCAN_TDH1R_DATA5_PosPCAN_TDH1R_DATA5_MskPCAN_TDH1R_DATA5kPCAN_TDH1R_DATA6_PosPCAN_TDH1R_DATA6_MskPCAN_TDH1R_DATA6jPCAN_TDH1R_DATA7_PosPCAN_TDH1R_DATA7_MskPCAN_TDH1R_DATA7iPCAN_TI2R_TXRQ_PosPCAN_TI2R_TXRQ_MskPCAN_TI2R_TXRQPCAN_TI2R_RTR_PosqPCAN_TI2R_RTR_MskxP CAN_TI2R_RTR PCAN_TI2R_IDE_PosPCAN_TI2R_IDE_MskP CAN_TI2R_IDE0PCAN_TI2R_EXID_Pos=PCAN_TI2R_EXID_MskDPCAN_TI2R_EXIDPCAN_TI2R_STID_Pos3PCAN_TI2R_STID_Msk:PCAN_TI2R_STIDPCAN_TDT2R_DLC_PosEPCAN_TDT2R_DLC_MskLPCAN_TDT2R_DLCPCAN_TDT2R_TGT_Pos)PCAN_TDT2R_TGT_Msk0PCAN_TDT2R_TGTPCAN_TDT2R_TIME_PosPCAN_TDT2R_TIME_MskPCAN_TDT2R_TIMEPCAN_TDL2R_DATA0_PosPCAN_TDL2R_DATA0_MskPCAN_TDL2R_DATA0kPCAN_TDL2R_DATA1_PosPCAN_TDL2R_DATA1_MskPCAN_TDL2R_DATA1jPCAN_TDL2R_DATA2_PosPCAN_TDL2R_DATA2_MskPCAN_TDL2R_DATA2iPCAN_TDL2R_DATA3_PosPCAN_TDL2R_DATA3_MskPCAN_TDL2R_DATA3hPCAN_TDH2R_DATA4_PosPCAN_TDH2R_DATA4_MskPCAN_TDH2R_DATA4kPCAN_TDH2R_DATA5_PosPCAN_TDH2R_DATA5_MskPCAN_TDH2R_DATA5jPCAN_TDH2R_DATA6_PosPCAN_TDH2R_DATA6_MskPCAN_TDH2R_DATA6iPCAN_TDH2R_DATA7_PosPCAN_TDH2R_DATA7_MskPCAN_TDH2R_DATA7hPCAN_RI0R_RTR_PosuPCAN_RI0R_RTR_Msk|P CAN_RI0R_RTRPCAN_RI0R_IDE_PosPCAN_RI0R_IDE_MskP CAN_RI0R_IDE4PCAN_RI0R_EXID_PosAPCAN_RI0R_EXID_MskHPCAN_RI0R_EXIDPCAN_RI0R_STID_Pos7PCAN_RI0R_STID_Msk>PCAN_RI0R_STIDPCAN_RDT0R_DLC_PosIPCAN_RDT0R_DLC_MskPPCAN_RDT0R_DLCPCAN_RDT0R_FMI_Pos@PCAN_RDT0R_FMI_MskGPCAN_RDT0R_FMIPCAN_RDT0R_TIME_PosPCAN_RDT0R_TIME_MskPCAN_RDT0R_TIMEPCAN_RDL0R_DATA0_PosPCAN_RDL0R_DATA0_MskPCAN_RDL0R_DATA0oPCAN_RDL0R_DATA1_PosPCAN_RDL0R_DATA1_MskPCAN_RDL0R_DATA1nPCAN_RDL0R_DATA2_PosPCAN_RDL0R_DATA2_MskPCAN_RDL0R_DATA2mPCAN_RDL0R_DATA3_PosPCAN_RDL0R_DATA3_MskPCAN_RDL0R_DATA3lPCAN_RDH0R_DATA4_PosPCAN_RDH0R_DATA4_MskPCAN_RDH0R_DATA4oPCAN_RDH0R_DATA5_PosPCAN_RDH0R_DATA5_MskPCAN_RDH0R_DATA5nPCAN_RDH0R_DATA6_PosPCAN_RDH0R_DATA6_MskPCAN_RDH0R_DATA6mPCAN_RDH0R_DATA7_PosPCAN_RDH0R_DATA7_MskPCAN_RDH0R_DATA7lPCAN_RI1R_RTR_PostPCAN_RI1R_RTR_Msk{P CAN_RI1R_RTR PCAN_RI1R_IDE_PosPCAN_RI1R_IDE_MskP CAN_RI1R_IDE3PCAN_RI1R_EXID_Pos@PCAN_RI1R_EXID_MskGPCAN_RI1R_EXIDPCAN_RI1R_STID_Pos6PCAN_RI1R_STID_Msk=PCAN_RI1R_STIDPCAN_RDT1R_DLC_PosHPCAN_RDT1R_DLC_MskOPCAN_RDT1R_DLCPCAN_RDT1R_FMI_Pos?PCAN_RDT1R_FMI_MskFPCAN_RDT1R_FMIPCAN_RDT1R_TIME_PosPCAN_RDT1R_TIME_MskPCAN_RDT1R_TIMEPCAN_RDL1R_DATA0_PosPCAN_RDL1R_DATA0_MskPCAN_RDL1R_DATA0nPCAN_RDL1R_DATA1_PosPCAN_RDL1R_DATA1_MskPCAN_RDL1R_DATA1mPCAN_RDL1R_DATA2_PosPCAN_RDL1R_DATA2_MskPCAN_RDL1R_DATA2lPCAN_RDL1R_DATA3_PosPCAN_RDL1R_DATA3_MskPCAN_RDL1R_DATA3kPCAN_RDH1R_DATA4_PosPCAN_RDH1R_DATA4_MskPCAN_RDH1R_DATA4nPCAN_RDH1R_DATA5_PosPCAN_RDH1R_DATA5_MskPCAN_RDH1R_DATA5mPCAN_RDH1R_DATA6_PosPCAN_RDH1R_DATA6_MskPCAN_RDH1R_DATA6lPCAN_RDH1R_DATA7_PosPCAN_RDH1R_DATA7_MskPCAN_RDH1R_DATA7kPCAN_FMR_FINIT_Pos)PCAN_FMR_FINIT_Msk0PCAN_FMR_FINITPCAN_FMR_CAN2SB_PosPCAN_FMR_CAN2SB_MskPCAN_FMR_CAN2SBPCAN_FM1R_FBM_PosPCAN_FM1R_FBM_MskP CAN_FM1R_FBM8PCAN_FM1R_FBM0_PosmPCAN_FM1R_FBM0_MsktPCAN_FM1R_FBM0PCAN_FM1R_FBM1_PoslPCAN_FM1R_FBM1_MsksPCAN_FM1R_FBM1PCAN_FM1R_FBM2_PoskPCAN_FM1R_FBM2_MskrPCAN_FM1R_FBM2PCAN_FM1R_FBM3_PosjPCAN_FM1R_FBM3_MskqPCAN_FM1R_FBM3PCAN_FM1R_FBM4_PosiPCAN_FM1R_FBM4_MskpPCAN_FM1R_FBM4PCAN_FM1R_FBM5_PoshPCAN_FM1R_FBM5_MskoPCAN_FM1R_FBM5PCAN_FM1R_FBM6_PosgPCAN_FM1R_FBM6_MsknPCAN_FM1R_FBM6PCAN_FM1R_FBM7_PosfPCAN_FM1R_FBM7_MskmPCAN_FM1R_FBM7PCAN_FM1R_FBM8_PosePCAN_FM1R_FBM8_MsklPCAN_FM1R_FBM8PCAN_FM1R_FBM9_PosdPCAN_FM1R_FBM9_MskkPCAN_FM1R_FBM9PCAN_FM1R_FBM10_Pos:PCAN_FM1R_FBM10_MskAPCAN_FM1R_FBM10PCAN_FM1R_FBM11_Pos9PCAN_FM1R_FBM11_Msk@PCAN_FM1R_FBM11PCAN_FM1R_FBM12_Pos8PCAN_FM1R_FBM12_Msk?PCAN_FM1R_FBM12PCAN_FM1R_FBM13_Pos7PCAN_FM1R_FBM13_Msk>PCAN_FM1R_FBM13PCAN_FS1R_FSC_PosPCAN_FS1R_FSC_MskP CAN_FS1R_FSC+PCAN_FS1R_FSC0_Pos`PCAN_FS1R_FSC0_MskgPCAN_FS1R_FSC0PCAN_FS1R_FSC1_Pos_PCAN_FS1R_FSC1_MskfPCAN_FS1R_FSC1PCAN_FS1R_FSC2_Pos^PCAN_FS1R_FSC2_MskePCAN_FS1R_FSC2PCAN_FS1R_FSC3_Pos]PCAN_FS1R_FSC3_MskdPCAN_FS1R_FSC3PCAN_FS1R_FSC4_Pos\PCAN_FS1R_FSC4_MskcPCAN_FS1R_FSC4PCAN_FS1R_FSC5_Pos[PCAN_FS1R_FSC5_MskbPCAN_FS1R_FSC5PCAN_FS1R_FSC6_PosZPCAN_FS1R_FSC6_MskaPCAN_FS1R_FSC6PCAN_FS1R_FSC7_PosYPCAN_FS1R_FSC7_Msk`PCAN_FS1R_FSC7PCAN_FS1R_FSC8_PosXPCAN_FS1R_FSC8_Msk_PCAN_FS1R_FSC8PCAN_FS1R_FSC9_PosWPCAN_FS1R_FSC9_Msk^PCAN_FS1R_FSC9PCAN_FS1R_FSC10_Pos-PCAN_FS1R_FSC10_Msk4PCAN_FS1R_FSC10PCAN_FS1R_FSC11_Pos,PCAN_FS1R_FSC11_Msk3PCAN_FS1R_FSC11PCAN_FS1R_FSC12_Pos+PCAN_FS1R_FSC12_Msk2PCAN_FS1R_FSC12PCAN_FS1R_FSC13_Pos*PCAN_FS1R_FSC13_Msk1PCAN_FS1R_FSC13PCAN_FFA1R_FFA_PoskPCAN_FFA1R_FFA_MskrPCAN_FFA1R_FFAPCAN_FFA1R_FFA0_Pos9PCAN_FFA1R_FFA0_Msk@PCAN_FFA1R_FFA0PCAN_FFA1R_FFA1_Pos8PCAN_FFA1R_FFA1_Msk?PCAN_FFA1R_FFA1PCAN_FFA1R_FFA2_Pos7PCAN_FFA1R_FFA2_Msk>PCAN_FFA1R_FFA2PCAN_FFA1R_FFA3_Pos6PCAN_FFA1R_FFA3_Msk=PCAN_FFA1R_FFA3PCAN_FFA1R_FFA4_Pos5PCAN_FFA1R_FFA4_Msk<PCAN_FFA1R_FFA4PCAN_FFA1R_FFA5_Pos4PCAN_FFA1R_FFA5_Msk;PCAN_FFA1R_FFA5PCAN_FFA1R_FFA6_Pos3PCAN_FFA1R_FFA6_Msk:PCAN_FFA1R_FFA6PCAN_FFA1R_FFA7_Pos2PCAN_FFA1R_FFA7_Msk9PCAN_FFA1R_FFA7PCAN_FFA1R_FFA8_Pos1PCAN_FFA1R_FFA8_Msk8PCAN_FFA1R_FFA8PCAN_FFA1R_FFA9_Pos0PCAN_FFA1R_FFA9_Msk7PCAN_FFA1R_FFA9PCAN_FFA1R_FFA10_PosPCAN_FFA1R_FFA10_Msk PCAN_FFA1R_FFA10PCAN_FFA1R_FFA11_PosPCAN_FFA1R_FFA11_Msk PCAN_FFA1R_FFA11PCAN_FFA1R_FFA12_PosPCAN_FFA1R_FFA12_Msk PCAN_FFA1R_FFA12PCAN_FFA1R_FFA13_PosPCAN_FFA1R_FFA13_Msk PCAN_FFA1R_FFA13PCAN_FA1R_FACT_Pos`PCAN_FA1R_FACT_MskgPCAN_FA1R_FACTPCAN_FA1R_FACT0_Pos.PCAN_FA1R_FACT0_Msk5PCAN_FA1R_FACT0PCAN_FA1R_FACT1_Pos-PCAN_FA1R_FACT1_Msk4PCAN_FA1R_FACT1PCAN_FA1R_FACT2_Pos,PCAN_FA1R_FACT2_Msk3PCAN_FA1R_FACT2PCAN_FA1R_FACT3_Pos+PCAN_FA1R_FACT3_Msk2PCAN_FA1R_FACT3PCAN_FA1R_FACT4_Pos*PCAN_FA1R_FACT4_Msk1PCAN_FA1R_FACT4PCAN_FA1R_FACT5_Pos)PCAN_FA1R_FACT5_Msk0PCAN_FA1R_FACT5PCAN_FA1R_FACT6_Pos(PCAN_FA1R_FACT6_Msk/PCAN_FA1R_FACT6PCAN_FA1R_FACT7_Pos'PCAN_FA1R_FACT7_Msk.PCAN_FA1R_FACT7PCAN_FA1R_FACT8_Pos&PCAN_FA1R_FACT8_Msk-PCAN_FA1R_FACT8PCAN_FA1R_FACT9_Pos%PCAN_FA1R_FACT9_Msk,PCAN_FA1R_FACT9PCAN_FA1R_FACT10_PosPCAN_FA1R_FACT10_MskPCAN_FA1R_FACT10PCAN_FA1R_FACT11_PosPCAN_FA1R_FACT11_MskPCAN_FA1R_FACT11PCAN_FA1R_FACT12_PosPCAN_FA1R_FACT12_MskPCAN_FA1R_FACT12PCAN_FA1R_FACT13_PosPCAN_FA1R_FACT13_MskPCAN_FA1R_FACT13PCAN_F0R1_FB0_PosPCAN_F0R1_FB0_MskP CAN_F0R1_FB0rPCAN_F0R1_FB1_PosPCAN_F0R1_FB1_MskP CAN_F0R1_FB1qPCAN_F0R1_FB2_PosPCAN_F0R1_FB2_MskP CAN_F0R1_FB2pPCAN_F0R1_FB3_PosPCAN_F0R1_FB3_MskP CAN_F0R1_FB3oPCAN_F0R1_FB4_PosPCAN_F0R1_FB4_MskP CAN_F0R1_FB4nPCAN_F0R1_FB5_PosPCAN_F0R1_FB5_MskP CAN_F0R1_FB5mPCAN_F0R1_FB6_PosPCAN_F0R1_FB6_MskP CAN_F0R1_FB6lPCAN_F0R1_FB7_PosPCAN_F0R1_FB7_MskP CAN_F0R1_FB7kPCAN_F0R1_FB8_PosPCAN_F0R1_FB8_MskP CAN_F0R1_FB8jPCAN_F0R1_FB9_PosPCAN_F0R1_FB9_MskP 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I2C_CR2_FREQBPI2C_CR2_FREQ_0PI2C_CR2_FREQ_1PI2C_CR2_FREQ_2PI2C_CR2_FREQ_3PI2C_CR2_FREQ_4PI2C_CR2_FREQ_5PI2C_CR2_ITERREN_PosPI2C_CR2_ITERREN_MskPI2C_CR2_ITERRENQPI2C_CR2_ITEVTEN_PosPI2C_CR2_ITEVTEN_MskPI2C_CR2_ITEVTENKPI2C_CR2_ITBUFEN_PosPI2C_CR2_ITBUFEN_MskPI2C_CR2_ITBUFEN]PI2C_CR2_DMAEN_PospPI2C_CR2_DMAEN_MskwPI2C_CR2_DMAEN PI2C_CR2_LAST_PosPI2C_CR2_LAST_MskP I2C_CR2_LAST<PI2C_OAR1_ADD1_7PI2C_OAR1_ADD8_9PI2C_OAR1_ADD0_PosPI2C_OAR1_ADD0_MskPI2C_OAR1_ADD0)PI2C_OAR1_ADD1_PosPI2C_OAR1_ADD1_MskPI2C_OAR1_ADD1(PI2C_OAR1_ADD2_PosPI2C_OAR1_ADD2_MskPI2C_OAR1_ADD2'PI2C_OAR1_ADD3_PosPI2C_OAR1_ADD3_MskPI2C_OAR1_ADD3&PI2C_OAR1_ADD4_PosPI2C_OAR1_ADD4_MskPI2C_OAR1_ADD4%PI2C_OAR1_ADD5_PosPI2C_OAR1_ADD5_MskPI2C_OAR1_ADD5$PI2C_OAR1_ADD6_PosPI2C_OAR1_ADD6_MskPI2C_OAR1_ADD6#PI2C_OAR1_ADD7_PosPI2C_OAR1_ADD7_MskPI2C_OAR1_ADD7"PI2C_OAR1_ADD8_PosPI2C_OAR1_ADD8_MskPI2C_OAR1_ADD8!PI2C_OAR1_ADD9_PosPI2C_OAR1_ADD9_MskPI2C_OAR1_ADD9 PI2C_OAR1_ADDMODE_PosPI2C_OAR1_ADDMODE_MskPI2C_OAR1_ADDMODE.PI2C_OAR2_ENDUAL_PosPI2C_OAR2_ENDUAL_MskPI2C_OAR2_ENDUALdPI2C_OAR2_ADD2_PosPI2C_OAR2_ADD2_MskPI2C_OAR2_ADD2&PI2C_DR_DR_PosxPI2C_DR_DR_MskP I2C_DR_DRPI2C_SR1_SB_Pos7PI2C_SR1_SB_Msk>P I2C_SR1_SBPI2C_SR1_ADDR_PosPI2C_SR1_ADDR_MskP I2C_SR1_ADDRFPI2C_SR1_BTF_PosPI2C_SR1_BTF_MskP I2C_SR1_BTFPI2C_SR1_ADD10_PosPI2C_SR1_ADD10_MskPI2C_SR1_ADD105PI2C_SR1_STOPF_Pos:PI2C_SR1_STOPF_MskAPI2C_SR1_STOPFPI2C_SR1_RXNE_PosPI2C_SR1_RXNE_MskP I2C_SR1_RXNE$PI2C_SR1_TXE_PosPI2C_SR1_TXE_MskP I2C_SR1_TXErPI2C_SR1_BERR_PosPI2C_SR1_BERR_MskP I2C_SR1_BERR6PI2C_SR1_ARLO_PosPI2C_SR1_ARLO_MskP I2C_SR1_ARLO3PI2C_SR1_AF_PosEPI2C_SR1_AF_MskLP I2C_SR1_AFPI2C_SR1_OVR_PosPI2C_SR1_OVR_MskP I2C_SR1_OVRlPI2C_SR1_PECERR_PosPI2C_SR1_PECERR_Msk PI2C_SR1_PECERRPI2C_SR1_TIMEOUT_PosPI2C_SR1_TIMEOUT_MskPI2C_SR1_TIMEOUT4PI2C_SR1_SMBALERT_PosfPI2C_SR1_SMBALERT_MskmPI2C_SR1_SMBALERTPI2C_SR2_MSL_PosPI2C_SR2_MSL_MskP I2C_SR2_MSLvPI2C_SR2_BUSY_PosPI2C_SR2_BUSY_MskP I2C_SR2_BUSYPI2C_SR2_TRA_PosPI2C_SR2_TRA_MskP I2C_SR2_TRA{PI2C_SR2_GENCALL_PosPI2C_SR2_GENCALL_MskPI2C_SR2_GENCALLdPI2C_SR2_SMBDEFAULT_PosPI2C_SR2_SMBDEFAULT_MskPI2C_SR2_SMBDEFAULTmPI2C_SR2_SMBHOST_PosPI2C_SR2_SMBHOST_MskPI2C_SR2_SMBHOST:PI2C_SR2_DUALF_PosYPI2C_SR2_DUALF_Msk`PI2C_SR2_DUALFPI2C_SR2_PEC_PosPI2C_SR2_PEC_MskP I2C_SR2_PECPI2C_CCR_CCR_PosPI2C_CCR_CCR_MskP I2C_CCR_CCRPI2C_CCR_DUTY_PosPI2C_CCR_DUTY_MskP I2C_CCR_DUTYPI2C_CCR_FS_Pos1PI2C_CCR_FS_Msk8P I2C_CCR_FSPI2C_TRISE_TRISE_PosPI2C_TRISE_TRISE_MskPI2C_TRISE_TRISE#PUSART_SR_PE_PosPUSART_SR_PE_MskP USART_SR_PE.PUSART_SR_FE_PosPUSART_SR_FE_MskP USART_SR_FE8PUSART_SR_NE_PosPUSART_SR_NE_MskP USART_SR_NE0PUSART_SR_ORE_PosBPUSART_SR_ORE_MskIP USART_SR_OREPUSART_SR_IDLE_PosPUSART_SR_IDLE_MskPUSART_SR_IDLEPUSART_SR_RXNE_PosPUSART_SR_RXNE_MskPUSART_SR_RXNEPUSART_SR_TC_PosPUSART_SR_TC_MskP USART_SR_TC,PUSART_SR_TXE_Pos7PUSART_SR_TXE_Msk>P USART_SR_TXEPUSART_SR_LBD_PosVPUSART_SR_LBD_Msk]P USART_SR_LBDPUSART_SR_CTS_Pos>PUSART_SR_CTS_MskEP USART_SR_CTSPUSART_DR_DR_PosPUSART_DR_DR_MskP USART_DR_DR<#PUSART_BRR_DIV_Fraction_Pos[#PUSART_BRR_DIV_Fraction_MskbPUSART_BRR_DIV_Fraction#PUSART_BRR_DIV_Mantissa_PosQ#PUSART_BRR_DIV_Mantissa_MskXPUSART_BRR_DIV_MantissaPUSART_CR1_SBK_Pos%PUSART_CR1_SBK_Msk,PUSART_CR1_SBKPUSART_CR1_RWU_PosPUSART_CR1_RWU_MskPUSART_CR1_RWUPUSART_CR1_RE_PospPUSART_CR1_RE_MskwP USART_CR1_RE PUSART_CR1_TE_PosnPUSART_CR1_TE_MskuP USART_CR1_TEPUSART_CR1_IDLEIE_PosSPUSART_CR1_IDLEIE_MskZPUSART_CR1_IDLEIEPUSART_CR1_RXNEIE_Pos4PUSART_CR1_RXNEIE_Msk;PUSART_CR1_RXNEIEPUSART_CR1_TCIE_PosPUSART_CR1_TCIE_MskPUSART_CR1_TCIEwPUSART_CR1_TXEIE_PosPUSART_CR1_TXEIE_MskPUSART_CR1_TXEIEPUSART_CR1_PEIE_PosPUSART_CR1_PEIE_MskPUSART_CR1_PEIEyPUSART_CR1_PS_PosdPUSART_CR1_PS_MskkP USART_CR1_PSPUSART_CR1_PCE_Pos-PUSART_CR1_PCE_Msk4PUSART_CR1_PCEPUSART_CR1_WAKE_PosPUSART_CR1_WAKE_MskPUSART_CR1_WAKEtPUSART_CR1_M_PosPUSART_CR1_M_MskP USART_CR1_MUPUSART_CR1_UE_PosmPUSART_CR1_UE_MsktP USART_CR1_UEPUSART_CR2_ADD_Pos;PUSART_CR2_ADD_MskBPUSART_CR2_ADDPUSART_CR2_LBDL_PosPUSART_CR2_LBDL_MskPUSART_CR2_LBDL}PUSART_CR2_LBDIE_PosPUSART_CR2_LBDIE_MskPUSART_CR2_LBDIE9PUSART_CR2_LBCL_PosPUSART_CR2_LBCL_MskPUSART_CR2_LBCL~PUSART_CR2_CPHA_PosPUSART_CR2_CPHA_MskPUSART_CR2_CPHAPUSART_CR2_CPOL_PosPUSART_CR2_CPOL_MskPUSART_CR2_CPOLmPUSART_CR2_CLKEN_PosPUSART_CR2_CLKEN_MskPUSART_CR2_CLKEN,PUSART_CR2_STOP_PosPUSART_CR2_STOP_MskPUSART_CR2_STOPUPUSART_CR2_STOP_0PUSART_CR2_STOP_1PUSART_CR2_LINEN_PosPUSART_CR2_LINEN_MskPUSART_CR2_LINEN#PUSART_CR3_EIE_Pos0PUSART_CR3_EIE_Msk7PUSART_CR3_EIEPUSART_CR3_IREN_PosPUSART_CR3_IREN_MskPUSART_CR3_IRENlPUSART_CR3_IRLP_PosPUSART_CR3_IRLP_MskPUSART_CR3_IRLPcPUSART_CR3_HDSEL_PosPUSART_CR3_HDSEL_MskPUSART_CR3_HDSEL(PUSART_CR3_NACK_PosPUSART_CR3_NACK_MskPUSART_CR3_NACK}PUSART_CR3_SCEN_PosPUSART_CR3_SCEN_MskPUSART_CR3_SCENqPUSART_CR3_DMAR_PosPUSART_CR3_DMAR_MskPUSART_CR3_DMARvPUSART_CR3_DMAT_PosPUSART_CR3_DMAT_MskPUSART_CR3_DMATtPUSART_CR3_RTSE_PosPUSART_CR3_RTSE_MskPUSART_CR3_RTSE\PUSART_CR3_CTSE_PosPUSART_CR3_CTSE_MskPUSART_CR3_CTSEkPUSART_CR3_CTSIE_PosPUSART_CR3_CTSIE_MskPUSART_CR3_CTSIE PUSART_GTPR_PSC_PosPUSART_GTPR_PSC_MskPUSART_GTPR_PSC?PUSART_GTPR_PSC_0PUSART_GTPR_PSC_1PUSART_GTPR_PSC_2PUSART_GTPR_PSC_3PUSART_GTPR_PSC_4PUSART_GTPR_PSC_5PUSART_GTPR_PSC_6PUSART_GTPR_PSC_7PUSART_GTPR_GT_PosPUSART_GTPR_GT_MskPUSART_GTPR_GT!PDBGMCU_IDCODE_DEV_ID_Pos'!PDBGMCU_IDCODE_DEV_ID_Msk.PDBGMCU_IDCODE_DEV_ID!PDBGMCU_IDCODE_REV_ID_Pos!PDBGMCU_IDCODE_REV_ID_Msk PDBGMCU_IDCODE_REV_IDPDBGMCU_IDCODE_REV_ID_0PDBGMCU_IDCODE_REV_ID_1PDBGMCU_IDCODE_REV_ID_2PDBGMCU_IDCODE_REV_ID_3PDBGMCU_IDCODE_REV_ID_4PDBGMCU_IDCODE_REV_ID_5PDBGMCU_IDCODE_REV_ID_6PDBGMCU_IDCODE_REV_ID_7PDBGMCU_IDCODE_REV_ID_8PDBGMCU_IDCODE_REV_ID_9 PDBGMCU_IDCODE_REV_ID_10 PDBGMCU_IDCODE_REV_ID_11 PDBGMCU_IDCODE_REV_ID_12 PDBGMCU_IDCODE_REV_ID_13 PDBGMCU_IDCODE_REV_ID_14 PDBGMCU_IDCODE_REV_ID_15 PDBGMCU_CR_DBG_SLEEP_Posb PDBGMCU_CR_DBG_SLEEP_MskiPDBGMCU_CR_DBG_SLEEPPDBGMCU_CR_DBG_STOP_PosPDBGMCU_CR_DBG_STOP_MskPDBGMCU_CR_DBG_STOP0"PDBGMCU_CR_DBG_STANDBY_Pos"PDBGMCU_CR_DBG_STANDBY_MskPDBGMCU_CR_DBG_STANDBY[!PDBGMCU_CR_TRACE_IOEN_Pos !PDBGMCU_CR_TRACE_IOEN_MskPDBGMCU_CR_TRACE_IOEN!PDBGMCU_CR_TRACE_MODE_Pos!PDBGMCU_CR_TRACE_MODE_MskPDBGMCU_CR_TRACE_MODEPDBGMCU_CR_TRACE_MODE_0PDBGMCU_CR_TRACE_MODE_1$PDBGMCU_CR_DBG_IWDG_STOP_Pos$PDBGMCU_CR_DBG_IWDG_STOP_Msk PDBGMCU_CR_DBG_IWDG_STOP$PDBGMCU_CR_DBG_WWDG_STOP_Pos$PDBGMCU_CR_DBG_WWDG_STOP_Msk PDBGMCU_CR_DBG_WWDG_STOP$PDBGMCU_CR_DBG_TIM1_STOP_Pos$PDBGMCU_CR_DBG_TIM1_STOP_Msk PDBGMCU_CR_DBG_TIM1_STOP$PDBGMCU_CR_DBG_TIM2_STOP_Pos$PDBGMCU_CR_DBG_TIM2_STOP_Msk PDBGMCU_CR_DBG_TIM2_STOP$PDBGMCU_CR_DBG_TIM3_STOP_Pos$PDBGMCU_CR_DBG_TIM3_STOP_Msk PDBGMCU_CR_DBG_TIM3_STOP$PDBGMCU_CR_DBG_TIM4_STOP_Pos$PDBGMCU_CR_DBG_TIM4_STOP_Msk PDBGMCU_CR_DBG_TIM4_STOP$PDBGMCU_CR_DBG_CAN1_STOP_Pos+$PDBGMCU_CR_DBG_CAN1_STOP_Msk2 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RDP_KEY_MskPRDP_KEYPFLASH_KEY1_Pos7PFLASH_KEY1_Msk>P FLASH_KEY1PFLASH_KEY2_Pos6PFLASH_KEY2_Msk=P FLASH_KEY2"PFLASH_OPTKEYR_OPTKEYR_Pos"PFLASH_OPTKEYR_OPTKEYR_MskPFLASH_OPTKEYR_OPTKEYRPFLASH_OPTKEY1PFLASH_OPTKEY2PFLASH_SR_BSY_Pos[PFLASH_SR_BSY_MskbP FLASH_SR_BSYPFLASH_SR_PGERR_PosPFLASH_SR_PGERR_MskPFLASH_SR_PGERR^PFLASH_SR_WRPRTERR_PosPFLASH_SR_WRPRTERR_MskPFLASH_SR_WRPRTERRPPFLASH_SR_EOP_PosePFLASH_SR_EOP_MsklP FLASH_SR_EOPPFLASH_CR_PG_PosPFLASH_CR_PG_MskP FLASH_CR_PG]PFLASH_CR_PER_PosrPFLASH_CR_PER_MskyP FLASH_CR_PER PFLASH_CR_MER_PosuPFLASH_CR_MER_Msk|P FLASH_CR_MERPFLASH_CR_OPTPG_PosPFLASH_CR_OPTPG_MskPFLASH_CR_OPTPGdPFLASH_CR_OPTER_PosPFLASH_CR_OPTER_MskPFLASH_CR_OPTERdPFLASH_CR_STRT_Pos PFLASH_CR_STRT_MskPFLASH_CR_STRTPFLASH_CR_LOCK_Pos.PFLASH_CR_LOCK_Msk5PFLASH_CR_LOCKPFLASH_CR_OPTWRE_PosrPFLASH_CR_OPTWRE_MskyPFLASH_CR_OPTWRE PFLASH_CR_ERRIE_PosPFLASH_CR_ERRIE_MskPFLASH_CR_ERRIEwPFLASH_CR_EOPIE_PosPFLASH_CR_EOPIE_MskPFLASH_CR_EOPIE|PFLASH_AR_FAR_PosPFLASH_AR_FAR_MskP FLASH_AR_FARPFLASH_OBR_OPTERR_Pos'PFLASH_OBR_OPTERR_Msk.PFLASH_OBR_OPTERRPFLASH_OBR_RDPRT_PosyPFLASH_OBR_RDPRT_MskPFLASH_OBR_RDPRTPFLASH_OBR_IWDG_SW_PosPFLASH_OBR_IWDG_SW_MskPFLASH_OBR_IWDG_SWf PFLASH_OBR_nRST_STOP_Pos PFLASH_OBR_nRST_STOP_MskPFLASH_OBR_nRST_STOP!PFLASH_OBR_nRST_STDBY_Pos!PFLASH_OBR_nRST_STDBY_MskPFLASH_OBR_nRST_STDBYHPFLASH_OBR_USER_PosPFLASH_OBR_USER_MskPFLASH_OBR_USERaPFLASH_OBR_DATA0_PosPFLASH_OBR_DATA0_MskPFLASH_OBR_DATA0TPFLASH_OBR_DATA1_PosPFLASH_OBR_DATA1_MskPFLASH_OBR_DATA1SPFLASH_WRPR_WRP_PosPFLASH_WRPR_WRP_MskPFLASH_WRPR_WRP?PFLASH_RDP_RDP_Pos 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PFLASH_WRP3_nWRP3_Msk'PFLASH_WRP3_nWRP3PIS_ADC_ALL_INSTANCE)P!IS_ADC_MULTIMODE_MASTER_INSTANCEPIS_ADC_COMMON_INSTANCE'PIS_ADC_DMA_CAPABILITY_INSTANCEPIS_CAN_ALL_INSTANCEPIS_CRC_ALL_INSTANCEPIS_DAC_ALL_INSTANCEPIS_DMA_ALL_INSTANCEPIS_GPIO_ALL_INSTANCEPIS_GPIO_AF_INSTANCEPIS_GPIO_LOCK_INSTANCE;PIS_I2C_ALL_INSTANCEPIS_SMBUS_ALL_INSTANCE0PIS_I2S_ALL_INSTANCEPIS_IWDG_ALL_INSTANCEPIS_SDIO_ALL_INSTANCEPIS_SPI_ALL_INSTANCEPIS_TIM_INSTANCE!PIS_TIM_ADVANCED_INSTANCEmPIS_TIM_CC1_INSTANCEPIS_TIM_CC2_INSTANCEPIS_TIM_CC3_INSTANCEPIS_TIM_CC4_INSTANCE-P%IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE-P%IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(P IS_TIM_CLOCKSOURCE_TIX_INSTANCE)P!IS_TIM_CLOCKSOURCE_ITRX_INSTANCE%PIS_TIM_OCXREF_CLEAR_INSTANCE*P"IS_TIM_ENCODER_INTERFACE_INSTANCEPIS_TIM_XOR_INSTANCEPIS_TIM_MASTER_INSTANCEPIS_TIM_SLAVE_INSTANCE. PIS_TIM_SYNCHRO_INSTANCE!PIS_TIM_DMABURST_INSTANCEAPIS_TIM_BREAK_INSTANCEDPIS_TIM_CCX_INSTANCEPIS_TIM_CCXN_INSTANCE,P$IS_TIM_COUNTER_MODE_SELECT_INSTANCE+P#IS_TIM_REPETITION_COUNTER_INSTANCE 'PIS_TIM_CLOCK_DIVISION_INSTANCEgPIS_TIM_DMA_INSTANCEPIS_TIM_DMA_CC_INSTANCE*P"IS_TIM_COMMUTATION_EVENT_INSTANCE`PIS_TIM_ETR_INSTANCE.P&IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE?$PIS_TIM_32B_COUNTER_INSTANCEwPIS_USART_INSTANCEkPIS_UART_INSTANCE$PIS_UART_HALFDUPLEX_INSTANCE^PIS_UART_LIN_INSTANCEv PIS_UART_HWFLOW_INSTANCE|PIS_SMARTCARD_INSTANCEQPIS_IRDA_INSTANCE(P IS_UART_MULTIPROCESSOR_INSTANCEPIS_UART_DMA_INSTANCEPIS_RTC_ALL_INSTANCEPIS_WWDG_ALL_INSTANCEPIS_PCD_ALL_INSTANCEP RCC_HSE_MIN[P RCC_HSE_MAXYPRCC_MAX_FREQUENCY{P ADC1_IRQnPDMA2_Channel4_IRQnP TIM9_IRQnPTIM1_BRK_TIM9_IRQnPTIM1_BRK_TIM15_IRQn PTIM1_TRG_COM_TIM11_IRQnP TIM11_IRQn PTIM1_TRG_COM_TIM17_IRQnP TIM10_IRQnPTIM1_UP_TIM16_IRQnPTIM1_UP_TIM10_IRQn%PTIM6_DAC_IRQnP TIM12_IRQnPTIM8_BRK_TIM12_IRQn PTIM8_TRG_COM_TIM14_IRQnP TIM14_IRQnPTIM8_UP_TIM13_IRQnP TIM13_IRQnP CEC_IRQn7POTG_FS_WKUP_IRQnjP USB_HP_IRQnP CAN1_TX_IRQnP USB_LP_IRQnPCAN1_RX0_IRQnPADC1_IRQHandler!PDMA2_Channel4_IRQHandlerBPTIM9_IRQHandler!PTIM1_BRK_TIM9_IRQHandler"PTIM1_BRK_TIM15_IRQHandler&PTIM1_TRG_COM_TIM11_IRQHandler8PTIM11_IRQHandlerV&PTIM1_TRG_COM_TIM17_IRQHandler2PTIM10_IRQHandlerW!PTIM1_UP_TIM16_IRQHandler!PTIM1_UP_TIM10_IRQHandlerPTIM6_DAC_IRQHandlerUPTIM12_IRQHandlerU"PTIM8_BRK_TIM12_IRQHandler&PTIM8_TRG_COM_TIM14_IRQHandler.PTIM14_IRQHandlerS!PTIM8_UP_TIM13_IRQHandlerPTIM13_IRQHandlerTPCEC_IRQHandlerPOTG_FS_WKUP_IRQHandlerPUSB_HP_IRQHandlerPCAN1_TX_IRQHandlerPUSB_LP_IRQHandlerPCAN1_RX0_IRQHandler`RESETp SET  FlagStatus ITStatusDISABLEENABLEJFunctionalStatePIS_FUNCTIONAL_STATESUCCESSERRORi ErrorStatus]PSET_BITP CLEAR_BITP READ_BITaP CLEAR_REGP WRITE_REGP READ_REGbP MODIFY_REGP POSITION_VALP__STM32F1xx_HAL_HPP__STM32F1xx_HAL_CONF_HPHAL_MODULE_ENABLEDcPHAL_ADC_MODULE_ENABLED4PHAL_CAN_MODULE_ENABLED*PHAL_CEC_MODULE_ENABLED1"PHAL_CORTEX_MODULE_ENABLED!PHAL_CRC_MODULE_ENABLED$PHAL_DAC_MODULE_ENABLED4PHAL_DMA_MODULE_ENABLED*PHAL_ETH_MODULE_ENABLED PHAL_EXTI_MODULE_ENABLED!PHAL_FLASH_MODULE_ENABLED PHAL_GPIO_MODULE_ENABLEDPHAL_HCD_MODULE_ENABLED-PHAL_I2C_MODULE_ENABLED>PHAL_I2S_MODULE_ENABLED. PHAL_IRDA_MODULE_ENABLED PHAL_IWDG_MODULE_ENABLED PHAL_NAND_MODULE_ENABLEDPHAL_NOR_MODULE_ENABLED "PHAL_PCCARD_MODULE_ENABLEDIPHAL_PCD_MODULE_ENABLED%PHAL_PWR_MODULE_ENABLEDPHAL_RCC_MODULE_ENABLED$PHAL_RTC_MODULE_ENABLEDPHAL_SD_MODULE_ENABLEDg%PHAL_SMARTCARD_MODULE_ENABLEDOPHAL_SPI_MODULE_ENABLED PHAL_SRAM_MODULE_ENABLEDPHAL_TIM_MODULE_ENABLED PHAL_UART_MODULE_ENABLED!PHAL_USART_MODULE_ENABLEDi PHAL_WWDG_MODULE_ENABLEDPHAL_MMC_MODULE_ENABLEDP HSE_VALUEPHSE_STARTUP_TIMEOUTP HSI_VALUEP LSI_VALUEP LSE_VALUEPLSE_STARTUP_TIMEOUTP VDD_VALUEPTICK_INT_PRIORITYSP USE_RTOS'PPREFETCH_ENABLEV'PUSE_HAL_ADC_REGISTER_CALLBACKS'PUSE_HAL_CAN_REGISTER_CALLBACKS'PUSE_HAL_CEC_REGISTER_CALLBACKS'PUSE_HAL_DAC_REGISTER_CALLBACKS'PUSE_HAL_ETH_REGISTER_CALLBACKS'PUSE_HAL_HCD_REGISTER_CALLBACKS'PUSE_HAL_I2C_REGISTER_CALLBACKS'PUSE_HAL_I2S_REGISTER_CALLBACKS'PUSE_HAL_MMC_REGISTER_CALLBACKS(P USE_HAL_NAND_REGISTER_CALLBACKSI'PUSE_HAL_NOR_REGISTER_CALLBACKS}*P"USE_HAL_PCCARD_REGISTER_CALLBACKS'PUSE_HAL_PCD_REGISTER_CALLBACKS'PUSE_HAL_RTC_REGISTER_CALLBACKS&PUSE_HAL_SD_REGISTER_CALLBACKS-P%USE_HAL_SMARTCARD_REGISTER_CALLBACKS(P USE_HAL_IRDA_REGISTER_CALLBACKSJ(P USE_HAL_SRAM_REGISTER_CALLBACKS7'PUSE_HAL_SPI_REGISTER_CALLBACKS'PUSE_HAL_TIM_REGISTER_CALLBACKS(P USE_HAL_UART_REGISTER_CALLBACKS.)P!USE_HAL_USART_REGISTER_CALLBACKS(P USE_HAL_WWDG_REGISTER_CALLBACKS1P MAC_ADDR0>P MAC_ADDR1=P MAC_ADDR2<P MAC_ADDR3;P MAC_ADDR4:P MAC_ADDR59PETH_RX_BUF_SIZEPETH_TX_BUF_SIZEP ETH_RXBUFNB^P ETH_TXBUFNB\PDP83848_PHY_ADDRESSMPPHY_RESET_DELAY PPHY_CONFIG_DELAYP PHY_READ_TOGP PHY_WRITE_TOPPHY_BCRPPHY_BSRP PHY_RESETP PHY_LOOPBACKPPHY_FULLDUPLEX_100MPPHY_HALFDUPLEX_100M+PPHY_FULLDUPLEX_10MEPPHY_HALFDUPLEX_10M]PPHY_AUTONEGOTIATION$PPHY_RESTART_AUTONEGOTIATIONGPPHY_POWERDOWNP PHY_ISOLATETPPHY_AUTONEGO_COMPLETE7PPHY_LINKED_STATUS_PPHY_JABBER_DETECTIONPPHY_SRP PHY_MICR@P PHY_MISR0PPHY_LINK_STATUSPPHY_SPEED_STATUSPPHY_DUPLEX_STATUSDPPHY_MICR_INT_ENPPHY_MICR_INT_OEPPHY_MISR_LINK_INT_ENOPPHY_LINK_INTERRUPTP USE_SPI_CRCFP__STM32F1xx_HAL_RCC_HP__STM32F1xx_HAL_DEFP __stddef_hP__STDDEF_DECLSm ptrdiff_t-size_tgwchar_t PNULLP __clang__6P offsetof_P__STDC_VERSION__z max_align_thHAL_OK# HAL_ERROR- HAL_BUSYv HAL_TIMEOUTHAL_StatusTypeDefv HAL_UNLOCKED\ HAL_LOCKEDHAL_LockTypeDefuPHAL_MAX_DELAYPHAL_IS_BIT_SETVPHAL_IS_BIT_CLRaP__HAL_LINKDMAPUNUSED!P__HAL_RESET_HANDLE_STATE;P __HAL_LOCKP __HAL_UNLOCKP __ALIGN_ENDVP__ALIGN_BEGINP __RAM_FUNCP __NOINLINE8 Q "T PLLState "T PLLSource< "TPLLMULRCC_PLLInitTypeDefy8 Q "T ClockType "T SYSCLKSource@ "TAHBCLKDivider "TAPB1CLKDivider "TAPB2CLKDividerRCC_ClkInitTypeDefGPRCC_PLLSOURCE_HSI_DIV2PRCC_PLLSOURCE_HSEz PRCC_OSCILLATORTYPE_NONEPRCC_OSCILLATORTYPE_HSEPRCC_OSCILLATORTYPE_HSIPRCC_OSCILLATORTYPE_LSEPRCC_OSCILLATORTYPE_LSIP RCC_HSE_OFFdP RCC_HSE_ONPRCC_HSE_BYPASSgP RCC_LSE_OFF`P RCC_LSE_ONPRCC_LSE_BYPASScP RCC_HSI_OFF`P RCC_HSI_ON#PRCC_HSICALIBRATION_DEFAULTP RCC_LSI_OFF\P RCC_LSI_ONP RCC_PLL_NONEP RCC_PLL_OFF\P RCC_PLL_ONPRCC_CLOCKTYPE_SYSCLKPRCC_CLOCKTYPE_HCLKAPRCC_CLOCKTYPE_PCLK1PRCC_CLOCKTYPE_PCLK2PRCC_SYSCLKSOURCE_HSIPRCC_SYSCLKSOURCE_HSE PRCC_SYSCLKSOURCE_PLLCLK$PRCC_SYSCLKSOURCE_STATUS_HSI.$PRCC_SYSCLKSOURCE_STATUS_HSE2'PRCC_SYSCLKSOURCE_STATUS_PLLCLKJPRCC_SYSCLK_DIV1*PRCC_SYSCLK_DIV2)PRCC_SYSCLK_DIV4'PRCC_SYSCLK_DIV8#PRCC_SYSCLK_DIV16PRCC_SYSCLK_DIV64PRCC_SYSCLK_DIV128PRCC_SYSCLK_DIV256PRCC_SYSCLK_DIV512PRCC_HCLK_DIV1PRCC_HCLK_DIV2PRCC_HCLK_DIV4PRCC_HCLK_DIV8PRCC_HCLK_DIV16 PRCC_RTCCLKSOURCE_NO_CLKPRCC_RTCCLKSOURCE_LSEPRCC_RTCCLKSOURCE_LSI$PRCC_RTCCLKSOURCE_HSE_DIV128P RCC_MCO1tPRCC_MCOP RCC_MCODIV_1*PRCC_IT_LSIRDYPRCC_IT_LSERDYPRCC_IT_HSIRDYPRCC_IT_HSERDYPRCC_IT_PLLRDYP RCC_IT_CSSPRCC_FLAG_HSIRDY*PRCC_FLAG_HSERDY.PRCC_FLAG_PLLRDY&PRCC_FLAG_LSIRDY&PRCC_FLAG_PINRSTPRCC_FLAG_PORRSTPRCC_FLAG_SFTRSTPRCC_FLAG_IWDGRSTPRCC_FLAG_WWDGRSTPRCC_FLAG_LPWRRSTPRCC_FLAG_LSERDY*"P__HAL_RCC_DMA1_CLK_ENABLE."P__HAL_RCC_SRAM_CLK_ENABLE#P__HAL_RCC_FLITF_CLK_ENABLE!P__HAL_RCC_CRC_CLK_ENABLE[#P__HAL_RCC_DMA1_CLK_DISABLE#P__HAL_RCC_SRAM_CLK_DISABLE$P__HAL_RCC_FLITF_CLK_DISABLEk"P__HAL_RCC_CRC_CLK_DISABLE &P__HAL_RCC_DMA1_IS_CLK_ENABLED'P__HAL_RCC_DMA1_IS_CLK_DISABLED&P__HAL_RCC_SRAM_IS_CLK_ENABLED'P__HAL_RCC_SRAM_IS_CLK_DISABLEDh'P__HAL_RCC_FLITF_IS_CLK_ENABLEDs(P __HAL_RCC_FLITF_IS_CLK_DISABLED$%P__HAL_RCC_CRC_IS_CLK_ENABLED&P__HAL_RCC_CRC_IS_CLK_DISABLED"P__HAL_RCC_TIM2_CLK_ENABLE"P__HAL_RCC_TIM3_CLK_ENABLE"P__HAL_RCC_WWDG_CLK_ENABLE$P__HAL_RCC_USART2_CLK_ENABLEl"P__HAL_RCC_I2C1_CLK_ENABLEB!P__HAL_RCC_BKP_CLK_ENABLEV!P__HAL_RCC_PWR_CLK_ENABLE:#P__HAL_RCC_TIM2_CLK_DISABLE#P__HAL_RCC_TIM3_CLK_DISABLE#P__HAL_RCC_WWDG_CLK_DISABLE%P__HAL_RCC_USART2_CLK_DISABLE#P__HAL_RCC_I2C1_CLK_DISABLE"P__HAL_RCC_BKP_CLK_DISABLE"P__HAL_RCC_PWR_CLK_DISABLE&P__HAL_RCC_TIM2_IS_CLK_ENABLED'P__HAL_RCC_TIM2_IS_CLK_DISABLED&P__HAL_RCC_TIM3_IS_CLK_ENABLED'P__HAL_RCC_TIM3_IS_CLK_DISABLED~&P__HAL_RCC_WWDG_IS_CLK_ENABLED'P__HAL_RCC_WWDG_IS_CLK_DISABLEDb(P __HAL_RCC_USART2_IS_CLK_ENABLED%)P!__HAL_RCC_USART2_IS_CLK_DISABLED&P__HAL_RCC_I2C1_IS_CLK_ENABLED'P__HAL_RCC_I2C1_IS_CLK_DISABLED%P__HAL_RCC_BKP_IS_CLK_ENABLED&P__HAL_RCC_BKP_IS_CLK_DISABLED%P__HAL_RCC_PWR_IS_CLK_ENABLED&P__HAL_RCC_PWR_IS_CLK_DISABLED"P__HAL_RCC_AFIO_CLK_ENABLE#P__HAL_RCC_GPIOA_CLK_ENABLE#P__HAL_RCC_GPIOB_CLK_ENABLE#P__HAL_RCC_GPIOC_CLK_ENABLE#P__HAL_RCC_GPIOD_CLK_ENABLE"P__HAL_RCC_ADC1_CLK_ENABLE8"P__HAL_RCC_TIM1_CLK_ENABLE"P__HAL_RCC_SPI1_CLK_ENABLE$P__HAL_RCC_USART1_CLK_ENABLEm#P__HAL_RCC_AFIO_CLK_DISABLE$P__HAL_RCC_GPIOA_CLK_DISABLEp$P__HAL_RCC_GPIOB_CLK_DISABLEo$P__HAL_RCC_GPIOC_CLK_DISABLEn$P__HAL_RCC_GPIOD_CLK_DISABLEm#P__HAL_RCC_ADC1_CLK_DISABLE#P__HAL_RCC_TIM1_CLK_DISABLE#P__HAL_RCC_SPI1_CLK_DISABLE%P__HAL_RCC_USART1_CLK_DISABLE&P__HAL_RCC_AFIO_IS_CLK_ENABLED'P__HAL_RCC_AFIO_IS_CLK_DISABLED|'P__HAL_RCC_GPIOA_IS_CLK_ENABLEDx(P __HAL_RCC_GPIOA_IS_CLK_DISABLED)'P__HAL_RCC_GPIOB_IS_CLK_ENABLEDw(P __HAL_RCC_GPIOB_IS_CLK_DISABLED('P__HAL_RCC_GPIOC_IS_CLK_ENABLEDv(P __HAL_RCC_GPIOC_IS_CLK_DISABLED''P__HAL_RCC_GPIOD_IS_CLK_ENABLEDu(P __HAL_RCC_GPIOD_IS_CLK_DISABLED&&P__HAL_RCC_ADC1_IS_CLK_ENABLED'P__HAL_RCC_ADC1_IS_CLK_DISABLED&P__HAL_RCC_TIM1_IS_CLK_ENABLED'P__HAL_RCC_TIM1_IS_CLK_DISABLED&P__HAL_RCC_SPI1_IS_CLK_ENABLED'P__HAL_RCC_SPI1_IS_CLK_DISABLED~(P __HAL_RCC_USART1_IS_CLK_ENABLED&)P!__HAL_RCC_USART1_IS_CLK_DISABLED#P__HAL_RCC_APB1_FORCE_RESET#P__HAL_RCC_TIM2_FORCE_RESET#P__HAL_RCC_TIM3_FORCE_RESET#P__HAL_RCC_WWDG_FORCE_RESET%P__HAL_RCC_USART2_FORCE_RESET#P__HAL_RCC_I2C1_FORCE_RESET"P__HAL_RCC_BKP_FORCE_RESET"P__HAL_RCC_PWR_FORCE_RESET%P__HAL_RCC_APB1_RELEASE_RESET$%P__HAL_RCC_TIM2_RELEASE_RESET %P__HAL_RCC_TIM3_RELEASE_RESET %P__HAL_RCC_WWDG_RELEASE_RESET'P__HAL_RCC_USART2_RELEASE_RESETc%P__HAL_RCC_I2C1_RELEASE_RESET9$P__HAL_RCC_BKP_RELEASE_RESETM$P__HAL_RCC_PWR_RELEASE_RESET1#P__HAL_RCC_APB2_FORCE_RESET#P__HAL_RCC_AFIO_FORCE_RESET$P__HAL_RCC_GPIOA_FORCE_RESETL$P__HAL_RCC_GPIOB_FORCE_RESETK$P__HAL_RCC_GPIOC_FORCE_RESETJ$P__HAL_RCC_GPIOD_FORCE_RESETI#P__HAL_RCC_ADC1_FORCE_RESET#P__HAL_RCC_TIM1_FORCE_RESET#P__HAL_RCC_SPI1_FORCE_RESET%P__HAL_RCC_USART1_FORCE_RESET%P__HAL_RCC_APB2_RELEASE_RESET#%P__HAL_RCC_AFIO_RELEASE_RESET &P__HAL_RCC_GPIOA_RELEASE_RESET&P__HAL_RCC_GPIOB_RELEASE_RESET&P__HAL_RCC_GPIOC_RELEASE_RESET&P__HAL_RCC_GPIOD_RELEASE_RESET%P__HAL_RCC_ADC1_RELEASE_RESET/%P__HAL_RCC_TIM1_RELEASE_RESET %P__HAL_RCC_SPI1_RELEASE_RESET 'P__HAL_RCC_USART1_RELEASE_RESETdP__HAL_RCC_HSI_ENABLEP__HAL_RCC_HSI_DISABLEA.P&__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUSTFP__HAL_RCC_LSI_ENABLEP__HAL_RCC_LSI_DISABLE=P__HAL_RCC_HSE_CONFIGP__HAL_RCC_LSE_CONFIGP__HAL_RCC_PLL_ENABLEP__HAL_RCC_PLL_DISABLE=P__HAL_RCC_PLL_CONFIG}$P__HAL_RCC_GET_PLL_OSCSOURCE0 P__HAL_RCC_SYSCLK_CONFIG$P__HAL_RCC_GET_SYSCLK_SOURCE$P__HAL_RCC_MCO1_CONFIGSP__HAL_RCC_RTC_CONFIG|!P__HAL_RCC_GET_RTC_SOURCEP__HAL_RCC_RTC_ENABLEP__HAL_RCC_RTC_DISABLE<$P__HAL_RCC_BACKUPRESET_FORCEe&P__HAL_RCC_BACKUPRESET_RELEASEP__HAL_RCC_ENABLE_ITP__HAL_RCC_DISABLE_ITP__HAL_RCC_CLEAR_ITP__HAL_RCC_GET_IT$P__HAL_RCC_CLEAR_RESET_FLAGSWP__HAL_RCC_GET_FLAG%!P__STM32F1xx_HAL_RCC_EX_HP CR_REG_INDEX PIS_RCC_HSE_PREDIVnPIS_RCC_PLL_MULHPIS_RCC_MCO1SOURCEPIS_RCC_ADCPLLCLK_DIVPIS_RCC_I2S2CLKSOURCEPIS_RCC_I2S3CLKSOURCEPIS_RCC_PERIPHCLOCKAPIS_RCC_USBPLLCLK_DIV8 Q "VOscillatorType "V HSEState "VHSEPredivValueY "V LSEState "V HSIState "VHSICalibrationValueM "V LSIState " VPLLRCC_OscInitTypeDef<8 Q "VPeriphClockSelection "VRTCClockSelection "VAdcClockSelection "VI2s2ClockSelection "VI2s3ClockSelection "VUsbClockSelection!RCC_PeriphCLKInitTypeDefPRCC_PERIPHCLK_RTCPRCC_PERIPHCLK_ADCPRCC_PERIPHCLK_I2S2oPRCC_PERIPHCLK_I2S3nPRCC_PERIPHCLK_USBPRCC_ADCPCLK2_DIV2PRCC_ADCPCLK2_DIV4PRCC_ADCPCLK2_DIV6PRCC_ADCPCLK2_DIV8!PRCC_I2S2CLKSOURCE_SYSCLK!PRCC_I2S3CLKSOURCE_SYSCLKPRCC_USBCLKSOURCE_PLL$PRCC_USBCLKSOURCE_PLL_DIV1_5{PRCC_HSE_PREDIV_DIV1PRCC_HSE_PREDIV_DIV2P RCC_PLL_MUL2P RCC_PLL_MUL3P RCC_PLL_MUL4P RCC_PLL_MUL5P RCC_PLL_MUL6P RCC_PLL_MUL7P RCC_PLL_MUL8P RCC_PLL_MUL9PRCC_PLL_MUL10PRCC_PLL_MUL11PRCC_PLL_MUL12PRCC_PLL_MUL13PRCC_PLL_MUL14PRCC_PLL_MUL15PRCC_PLL_MUL16PRCC_MCO1SOURCE_NOCLOCKPRCC_MCO1SOURCE_SYSCLKQPRCC_MCO1SOURCE_HSILPRCC_MCO1SOURCE_HSEPPRCC_MCO1SOURCE_PLLCLKh"P__HAL_RCC_DMA2_CLK_ENABLE-#P__HAL_RCC_DMA2_CLK_DISABLE"P__HAL_RCC_FSMC_CLK_ENABLE#P__HAL_RCC_FSMC_CLK_DISABLE"P__HAL_RCC_SDIO_CLK_ENABLE#P__HAL_RCC_SDIO_CLK_DISABLE&P__HAL_RCC_DMA2_IS_CLK_ENABLED'P__HAL_RCC_DMA2_IS_CLK_DISABLED&P__HAL_RCC_FSMC_IS_CLK_ENABLED'P__HAL_RCC_FSMC_IS_CLK_DISABLEDr&P__HAL_RCC_SDIO_IS_CLK_ENABLED'P__HAL_RCC_SDIO_IS_CLK_DISABLEDl"P__HAL_RCC_CAN1_CLK_ENABLE.#P__HAL_RCC_CAN1_CLK_DISABLE"P__HAL_RCC_TIM4_CLK_ENABLE"P__HAL_RCC_SPI2_CLK_ENABLE$P__HAL_RCC_USART3_CLK_ENABLEk"P__HAL_RCC_I2C2_CLK_ENABLEA#P__HAL_RCC_TIM4_CLK_DISABLE#P__HAL_RCC_SPI2_CLK_DISABLE%P__HAL_RCC_USART3_CLK_DISABLE#P__HAL_RCC_I2C2_CLK_DISABLE!P__HAL_RCC_USB_CLK_ENABLEI"P__HAL_RCC_USB_CLK_DISABLE"P__HAL_RCC_TIM5_CLK_ENABLE"P__HAL_RCC_TIM6_CLK_ENABLE"P__HAL_RCC_TIM7_CLK_ENABLE"P__HAL_RCC_SPI3_CLK_ENABLE#P__HAL_RCC_UART4_CLK_ENABLE#P__HAL_RCC_UART5_CLK_ENABLE!P__HAL_RCC_DAC_CLK_ENABLEk#P__HAL_RCC_TIM5_CLK_DISABLE#P__HAL_RCC_TIM6_CLK_DISABLE#P__HAL_RCC_TIM7_CLK_DISABLE#P__HAL_RCC_SPI3_CLK_DISABLE$P__HAL_RCC_UART4_CLK_DISABLEp$P__HAL_RCC_UART5_CLK_DISABLEo"P__HAL_RCC_DAC_CLK_DISABLEP STM32F100xE&P__HAL_RCC_CAN1_IS_CLK_ENABLED'P__HAL_RCC_CAN1_IS_CLK_DISABLED&P__HAL_RCC_TIM4_IS_CLK_ENABLED'P__HAL_RCC_TIM4_IS_CLK_DISABLED}&P__HAL_RCC_SPI2_IS_CLK_ENABLED'P__HAL_RCC_SPI2_IS_CLK_DISABLED}(P __HAL_RCC_USART3_IS_CLK_ENABLED$)P!__HAL_RCC_USART3_IS_CLK_DISABLED&P__HAL_RCC_I2C2_IS_CLK_ENABLED'P__HAL_RCC_I2C2_IS_CLK_DISABLED%P__HAL_RCC_USB_IS_CLK_ENABLED&P__HAL_RCC_USB_IS_CLK_DISABLED&P__HAL_RCC_TIM5_IS_CLK_ENABLED'P__HAL_RCC_TIM5_IS_CLK_DISABLED|&P__HAL_RCC_TIM6_IS_CLK_ENABLED'P__HAL_RCC_TIM6_IS_CLK_DISABLED{&P__HAL_RCC_TIM7_IS_CLK_ENABLED'P__HAL_RCC_TIM7_IS_CLK_DISABLEDz&P__HAL_RCC_SPI3_IS_CLK_ENABLED'P__HAL_RCC_SPI3_IS_CLK_DISABLED|'P__HAL_RCC_UART4_IS_CLK_ENABLEDx(P __HAL_RCC_UART4_IS_CLK_DISABLED)'P__HAL_RCC_UART5_IS_CLK_ENABLEDw(P __HAL_RCC_UART5_IS_CLK_DISABLED(%P__HAL_RCC_DAC_IS_CLK_ENABLED$&P__HAL_RCC_DAC_IS_CLK_DISABLED"P__HAL_RCC_ADC2_CLK_ENABLE7#P__HAL_RCC_ADC2_CLK_DISABLE#P__HAL_RCC_GPIOE_CLK_ENABLE$P__HAL_RCC_GPIOE_CLK_DISABLEl#P__HAL_RCC_GPIOF_CLK_ENABLE#P__HAL_RCC_GPIOG_CLK_ENABLE$P__HAL_RCC_GPIOF_CLK_DISABLEk$P__HAL_RCC_GPIOG_CLK_DISABLEj"P__HAL_RCC_TIM8_CLK_ENABLE"P__HAL_RCC_ADC3_CLK_ENABLE6#P__HAL_RCC_TIM8_CLK_DISABLE#P__HAL_RCC_ADC3_CLK_DISABLE&P__HAL_RCC_ADC2_IS_CLK_ENABLED'P__HAL_RCC_ADC2_IS_CLK_DISABLED'P__HAL_RCC_GPIOE_IS_CLK_ENABLEDt(P __HAL_RCC_GPIOE_IS_CLK_DISABLED%'P__HAL_RCC_GPIOF_IS_CLK_ENABLEDs(P __HAL_RCC_GPIOF_IS_CLK_DISABLED$'P__HAL_RCC_GPIOG_IS_CLK_ENABLEDr(P __HAL_RCC_GPIOG_IS_CLK_DISABLED#&P__HAL_RCC_TIM8_IS_CLK_ENABLED'P__HAL_RCC_TIM8_IS_CLK_DISABLEDy&P__HAL_RCC_ADC3_IS_CLK_ENABLED'P__HAL_RCC_ADC3_IS_CLK_DISABLED#P__HAL_RCC_CAN1_FORCE_RESET%P__HAL_RCC_CAN1_RELEASE_RESET%#P__HAL_RCC_TIM4_FORCE_RESET#P__HAL_RCC_SPI2_FORCE_RESET%P__HAL_RCC_USART3_FORCE_RESET#P__HAL_RCC_I2C2_FORCE_RESET%P__HAL_RCC_TIM4_RELEASE_RESET %P__HAL_RCC_SPI2_RELEASE_RESET 'P__HAL_RCC_USART3_RELEASE_RESETb%P__HAL_RCC_I2C2_RELEASE_RESET8"P__HAL_RCC_USB_FORCE_RESET$P__HAL_RCC_USB_RELEASE_RESET@#P__HAL_RCC_TIM5_FORCE_RESET#P__HAL_RCC_TIM6_FORCE_RESET#P__HAL_RCC_TIM7_FORCE_RESET#P__HAL_RCC_SPI3_FORCE_RESET$P__HAL_RCC_UART4_FORCE_RESETL$P__HAL_RCC_UART5_FORCE_RESETK"P__HAL_RCC_DAC_FORCE_RESET%P__HAL_RCC_TIM5_RELEASE_RESET %P__HAL_RCC_TIM6_RELEASE_RESET%P__HAL_RCC_TIM7_RELEASE_RESET%P__HAL_RCC_SPI3_RELEASE_RESET &P__HAL_RCC_UART4_RELEASE_RESET&P__HAL_RCC_UART5_RELEASE_RESET$P__HAL_RCC_DAC_RELEASE_RESETb#P__HAL_RCC_ADC2_FORCE_RESET%P__HAL_RCC_ADC2_RELEASE_RESET.$P__HAL_RCC_GPIOE_FORCE_RESETH&P__HAL_RCC_GPIOE_RELEASE_RESET$P__HAL_RCC_GPIOF_FORCE_RESETG$P__HAL_RCC_GPIOG_FORCE_RESETF&P__HAL_RCC_GPIOF_RELEASE_RESET&P__HAL_RCC_GPIOG_RELEASE_RESET#P__HAL_RCC_TIM8_FORCE_RESET#P__HAL_RCC_ADC3_FORCE_RESET%P__HAL_RCC_TIM8_RELEASE_RESET%P__HAL_RCC_ADC3_RELEASE_RESET-$P__HAL_RCC_HSE_PREDIV_CONFIGN!P__HAL_RCC_HSE_GET_PREDIV*P__HAL_RCC_USB_CONFIG{!P__HAL_RCC_GET_USB_SOURCEP__HAL_RCC_ADC_CONFIG!P__HAL_RCC_GET_ADC_SOURCE;,PeriphClkInit"HAL_RCCEx_PeriphCLKConfig,PeriphClkInit%HAL_RCCEx_GetPeriphCLKConfig,  PeriphClkK#HAL_RCCEx_GetPeriphCLKFreqHAL_RCC_DeInit$,RCC_OscInitStruct:HAL_RCC_OscConfig,RCC_ClkInitStructE,  FLatencyHAL_RCC_ClockConfig,  RCC_MCOxA, RCC_MCOSource>,  RCC_MCODivHAL_RCC_MCOConfig&HAL_RCC_EnableCSS+HAL_RCC_DisableCSS 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RCC_OFFSETPRCC_CR_OFFSETPRCC_CFGR_OFFSET.PRCC_CIR_OFFSETtPRCC_BDCR_OFFSET5PRCC_CSR_OFFSETjPRCC_CR_OFFSET_BBPRCC_CFGR_OFFSET_BBEPRCC_CIR_OFFSET_BBPRCC_BDCR_OFFSET_BBLPRCC_CSR_OFFSET_BBPRCC_HSION_BIT_NUMBERPRCC_CR_HSION_BBPRCC_HSEON_BIT_NUMBERPRCC_CR_HSEON_BB"PRCC_CSSON_BIT_NUMBERPRCC_CR_CSSON_BBPRCC_PLLON_BIT_NUMBERPRCC_CR_PLLON_BBPRCC_LSION_BIT_NUMBERPRCC_CSR_LSION_BBPRCC_RMVF_BIT_NUMBERPRCC_CSR_RMVF_BBPRCC_LSEON_BIT_NUMBERPRCC_BDCR_LSEON_BBPRCC_LSEBYP_BIT_NUMBER5PRCC_BDCR_LSEBYP_BBDPRCC_RTCEN_BIT_NUMBERPRCC_BDCR_RTCEN_BBPRCC_BDRST_BIT_NUMBERPRCC_BDCR_BDRST_BBPRCC_CR_BYTE2_ADDRESSPRCC_CIR_BYTE1_ADDRESScPRCC_CIR_BYTE2_ADDRESSbPBDCR_REG_INDEXPCSR_REG_INDEXPRCC_FLAG_MASK%P__HAL_RCC_SYSCFG_CLK_DISABLE$P__HAL_RCC_SYSCFG_CLK_ENABLE^%P__HAL_RCC_SYSCFG_FORCE_RESET'P__HAL_RCC_SYSCFG_RELEASE_RESETUPIS_RCC_PLLSOURCEPIS_RCC_OSCILLATORTYPE1P IS_RCC_HSEP IS_RCC_LSEP IS_RCC_HSI!PIS_RCC_CALIBRATION_VALUEeP IS_RCC_LSIP IS_RCC_PLLPIS_RCC_CLOCKTYPEPIS_RCC_SYSCLKSOURCE#PIS_RCC_SYSCLKSOURCE_STATUSxP IS_RCC_HCLKaP IS_RCC_PCLKYP IS_RCC_MCOPIS_RCC_MCODIVPIS_RCC_RTCCLKSOURCEPSTM32F1xx_HAL_GPIO_Hz8 Q "XPinu "XMode "XPull "XSpeedGPIO_InitTypeDefGPIO_PIN_RESET GPIO_PIN_SET%GPIO_PinState1P GPIO_PIN_0P GPIO_PIN_1P GPIO_PIN_2P GPIO_PIN_3P GPIO_PIN_4P GPIO_PIN_5P GPIO_PIN_6P GPIO_PIN_7P GPIO_PIN_8P GPIO_PIN_9P GPIO_PIN_10P GPIO_PIN_11P GPIO_PIN_12~P GPIO_PIN_13}P GPIO_PIN_14|P GPIO_PIN_15{P GPIO_PIN_AllPGPIO_PIN_MASKPGPIO_MODE_INPUT PGPIO_MODE_OUTPUT_PPPGPIO_MODE_OUTPUT_ODPGPIO_MODE_AF_PPPGPIO_MODE_AF_OD"PGPIO_MODE_AF_INPUTPGPIO_MODE_ANALOGPGPIO_MODE_IT_RISINGPGPIO_MODE_IT_FALLING$PGPIO_MODE_IT_RISING_FALLING_PGPIO_MODE_EVT_RISINGwPGPIO_MODE_EVT_FALLINGD%PGPIO_MODE_EVT_RISING_FALLING PGPIO_SPEED_FREQ_LOWPGPIO_SPEED_FREQ_MEDIUMPGPIO_SPEED_FREQ_HIGHP GPIO_NOPULLMP GPIO_PULLUPEPGPIO_PULLDOWN!P__HAL_GPIO_EXTI_GET_FLAG)#P__HAL_GPIO_EXTI_CLEAR_FLAGP__HAL_GPIO_EXTI_GET_IT!P__HAL_GPIO_EXTI_CLEAR_IT&P__HAL_GPIO_EXTI_GENERATE_SWIT PSTM32F1xx_HAL_GPIO_EX_HxPAFIO_EVENTOUT_PIN_0PAFIO_EVENTOUT_PIN_1PAFIO_EVENTOUT_PIN_2PAFIO_EVENTOUT_PIN_3PAFIO_EVENTOUT_PIN_4PAFIO_EVENTOUT_PIN_5PAFIO_EVENTOUT_PIN_6PAFIO_EVENTOUT_PIN_7PAFIO_EVENTOUT_PIN_8PAFIO_EVENTOUT_PIN_9PAFIO_EVENTOUT_PIN_10PAFIO_EVENTOUT_PIN_11PAFIO_EVENTOUT_PIN_12PAFIO_EVENTOUT_PIN_13PAFIO_EVENTOUT_PIN_14PAFIO_EVENTOUT_PIN_15PIS_AFIO_EVENTOUT_PINjPAFIO_EVENTOUT_PORT_AgPAFIO_EVENTOUT_PORT_BfPAFIO_EVENTOUT_PORT_CePAFIO_EVENTOUT_PORT_DdPAFIO_EVENTOUT_PORT_EcPIS_AFIO_EVENTOUT_PORT %P__HAL_AFIO_REMAP_SPI1_ENABLE,&P__HAL_AFIO_REMAP_SPI1_DISABLE%P__HAL_AFIO_REMAP_I2C1_ENABLEZ&P__HAL_AFIO_REMAP_I2C1_DISABLE 'P__HAL_AFIO_REMAP_USART1_ENABLE(P __HAL_AFIO_REMAP_USART1_DISABLE6'P__HAL_AFIO_REMAP_USART2_ENABLE(P __HAL_AFIO_REMAP_USART2_DISABLE5'P__HAL_AFIO_REMAP_USART3_ENABLE(P __HAL_AFIO_REMAP_USART3_PARTIAL(P __HAL_AFIO_REMAP_USART3_DISABLE4%P__HAL_AFIO_REMAP_TIM1_ENABLE.&P__HAL_AFIO_REMAP_TIM1_PARTIAL&P__HAL_AFIO_REMAP_TIM1_DISABLE%P__HAL_AFIO_REMAP_TIM2_ENABLE-(P __HAL_AFIO_REMAP_TIM2_PARTIAL_20(P __HAL_AFIO_REMAP_TIM2_PARTIAL_11&P__HAL_AFIO_REMAP_TIM2_DISABLE%P__HAL_AFIO_REMAP_TIM3_ENABLE,&P__HAL_AFIO_REMAP_TIM3_PARTIAL&P__HAL_AFIO_REMAP_TIM3_DISABLE%P__HAL_AFIO_REMAP_TIM4_ENABLE+&P__HAL_AFIO_REMAP_TIM4_DISABLE P__HAL_AFIO_REMAP_CAN1_1 P__HAL_AFIO_REMAP_CAN1_2 P__HAL_AFIO_REMAP_CAN1_3%P__HAL_AFIO_REMAP_PD01_ENABLET&P__HAL_AFIO_REMAP_PD01_DISABLE(P __HAL_AFIO_REMAP_TIM5CH4_ENABLEe)P!__HAL_AFIO_REMAP_TIM5CH4_DISABLE-P%__HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE.P&__HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE-P%__HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE.P&__HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE-P%__HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE.P&__HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE~-P%__HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE.P&__HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE$P__HAL_AFIO_REMAP_SWJ_ENABLEW&P__HAL_AFIO_REMAP_SWJ_NONJTRSTx$P__HAL_AFIO_REMAP_SWJ_NOJTAG;%P__HAL_AFIO_REMAP_SWJ_DISABLE)P!__HAL_AFIO_FSMCNADV_DISCONNECTED&P__HAL_AFIO_FSMCNADV_CONNECTEDPGPIO_GET_INDEXjPAFIO_REMAP_ENABLEPAFIO_REMAP_DISABLEaPAFIO_REMAP_PARTIALHPAFIO_DBGAFR_CONFIGn, GPIO_PortSource, GPIO_PinSource"HAL_GPIOEx_ConfigEventout"HAL_GPIOEx_EnableEventout#HAL_GPIOEx_DisableEventout',GPIOx , GPIO_InitHAL_GPIO_Initx,GPIOx ,  GPIO_PinHAL_GPIO_DeInit,GPIOx , GPIO_PinHAL_GPIO_ReadPinc,GPIOx , GPIO_Pin," PinStateHAL_GPIO_WritePin,GPIOx , GPIO_PinHAL_GPIO_TogglePiny,GPIOx , GPIO_PinHAL_GPIO_LockPinV, GPIO_Pin!HAL_GPIO_EXTI_IRQHandler, GPIO_PinHAL_GPIO_EXTI_CallbackTPIS_GPIO_PIN_ACTIONP IS_GPIO_PINEP IS_GPIO_MODEPIS_GPIO_SPEEDP IS_GPIO_PULLPSTM32F1xx_HAL_EXTI_HoHAL_EXTI_COMMON_CB_IDmEXTI_CallbackIDTypeDef8 Q "YLine "YPendingCallbackEXTI_HandleTypeDefG8 Q "YLine "YMode "YTrigger "YGPIOSelEXTI_ConfigTypeDef=P EXTI_LINE_0eP EXTI_LINE_1dP EXTI_LINE_2cP EXTI_LINE_3bP EXTI_LINE_4aP EXTI_LINE_5`P EXTI_LINE_6_P EXTI_LINE_7^P EXTI_LINE_8]P EXTI_LINE_9\P EXTI_LINE_102P EXTI_LINE_111P EXTI_LINE_120P EXTI_LINE_13/P EXTI_LINE_14.P EXTI_LINE_15-P EXTI_LINE_16,P EXTI_LINE_17+P EXTI_LINE_18*PEXTI_MODE_NONEbPEXTI_MODE_INTERRUPTPEXTI_MODE_EVENTPEXTI_TRIGGER_NONEmPEXTI_TRIGGER_RISINGPEXTI_TRIGGER_FALLING$PEXTI_TRIGGER_RISING_FALLINGaP EXTI_GPIOAP EXTI_GPIOBP EXTI_GPIOCP EXTI_GPIODP EXTI_GPIOEP EXTI_GPIOFP EXTI_GPIOGPEXTI_PROPERTY_SHIFTP EXTI_CONFIGfP EXTI_GPIOPEXTI_PROPERTY_MASKPEXTI_PIN_MASKPEXTI_MODE_MASKfPEXTI_TRIGGER_MASKqP EXTI_LINE_NBP IS_EXTI_LINEP IS_EXTI_MODEPIS_EXTI_TRIGGERPIS_EXTI_PENDING_EDGEPIS_EXTI_CONFIG_LINEPIS_EXTI_GPIO_PORTBPIS_EXTI_GPIO_PIN,hexti, pExtiConfig[HAL_EXTI_SetConfigLine,hexti, pExtiConfig[HAL_EXTI_GetConfigLine,hexti!HAL_EXTI_ClearConfigLine&,hexti," CallbackID, pPendingCbfn "HAL_EXTI_RegisterCallback,hexti,  ExtiLineHAL_EXTI_GetHandle,hextiHAL_EXTI_IRQHandlerK,hexti , EdgebHAL_EXTI_GetPending,hexti , EdgebHAL_EXTI_ClearPendingE,hextiHAL_EXTI_GenerateSWIP__STM32F1xx_HAL_DMA_H8 Q "Z Direction "Z PeriphInc "ZMemIncg "ZPeriphDataAlignment "ZMemDataAlignmentT "ZMode "Z Priority:DMA_InitTypeDefmHAL_DMA_STATE_RESETHAL_DMA_STATE_READYHAL_DMA_STATE_BUSYQHAL_DMA_STATE_TIMEOUTgHAL_DMA_StateTypeDefHAL_DMA_FULL_TRANSFERwHAL_DMA_HALF_TRANSFER%HAL_DMA_LevelCompleteTypeDef HAL_DMA_XFER_CPLT_CB_ID$HAL_DMA_XFER_HALFCPLT_CB_ID!HAL_DMA_XFER_ERROR_CB_IDz!HAL_DMA_XFER_ABORT_CB_IDHAL_DMA_XFER_ALL_CB_ID/"HAL_DMA_CallbackIDTypeDef8__DMA_HandleTypeDef "Z InstanceB "ZInit ""ZLock ""ZStateu "ZParent "ZXferCpltCallback2 "ZXferHalfCpltCallback "ZXferErrorCallback "ZXferAbortCallback "Z ErrorCode "ZDmaBaseAddress "Z ChannelIndexDMA_HandleTypeDefPHAL_DMA_ERROR_NONE)PHAL_DMA_ERROR_TEPHAL_DMA_ERROR_NO_XFER"PHAL_DMA_ERROR_TIMEOUT,$PHAL_DMA_ERROR_NOT_SUPPORTED1PDMA_PERIPH_TO_MEMORYpPDMA_MEMORY_TO_PERIPHpPDMA_MEMORY_TO_MEMORY_PDMA_PINC_ENABLELPDMA_PINC_DISABLEPDMA_MINC_ENABLEOPDMA_MINC_DISABLEPDMA_PDATAALIGN_BYTE PDMA_PDATAALIGN_HALFWORDPDMA_PDATAALIGN_WORDPDMA_MDATAALIGN_BYTE PDMA_MDATAALIGN_HALFWORDPDMA_MDATAALIGN_WORDP DMA_NORMALP DMA_CIRCULAR-PDMA_PRIORITY_LOWPDMA_PRIORITY_MEDIUMPDMA_PRIORITY_HIGHwPDMA_PRIORITY_VERY_HIGHP DMA_IT_TCP DMA_IT_HTP DMA_IT_TEP DMA_FLAG_GL1EP DMA_FLAG_TC1AP DMA_FLAG_HT1<P DMA_FLAG_TE1?P DMA_FLAG_GL2DP DMA_FLAG_TC2@P DMA_FLAG_HT2;P DMA_FLAG_TE2>P DMA_FLAG_GL3CP DMA_FLAG_TC3?P DMA_FLAG_HT3:P DMA_FLAG_TE3=P DMA_FLAG_GL4BP DMA_FLAG_TC4>P DMA_FLAG_HT49P DMA_FLAG_TE4<P DMA_FLAG_GL5AP DMA_FLAG_TC5=P DMA_FLAG_HT58P DMA_FLAG_TE5;P DMA_FLAG_GL6@P DMA_FLAG_TC6<P DMA_FLAG_HT67P DMA_FLAG_TE6:P DMA_FLAG_GL7?P DMA_FLAG_TC7;P DMA_FLAG_HT76P DMA_FLAG_TE79%P__HAL_DMA_RESET_HANDLE_STATEP__HAL_DMA_ENABLEP__HAL_DMA_DISABLEP__HAL_DMA_ENABLE_ITP__HAL_DMA_DISABLE_IT P__HAL_DMA_GET_IT_SOURCEnP__HAL_DMA_GET_COUNTER!P__STM32F1xx_HAL_DMA_EX_H$P__HAL_DMA_GET_TC_FLAG_INDEXL$P__HAL_DMA_GET_HT_FLAG_INDEXG$P__HAL_DMA_GET_TE_FLAG_INDEXJ$P__HAL_DMA_GET_GI_FLAG_INDEXSP__HAL_DMA_GET_FLAG+P__HAL_DMA_CLEAR_FLAG ,hdma/ HAL_DMA_Init ,hdma/HAL_DMA_DeInit* ,hdma/,  SrcAddress,  DstAddress,  DataLengthHAL_DMA_Start[ ,hdma/,  SrcAddress,  DstAddress,  DataLengthHAL_DMA_Start_ITY ,hdma/HAL_DMA_Abortq ,hdma/HAL_DMA_Abort_ITo ,hdma/, CompleteLevel, Timeout HAL_DMA_PollForTransferR ,hdma/HAL_DMA_IRQHandler ,hdma/," CallbackID, pCallbackB!HAL_DMA_RegisterCallback ,hdma/," CallbackID#HAL_DMA_UnRegisterCallback: ,hdma/HAL_DMA_GetStateB ,hdma/HAL_DMA_GetError9PIS_DMA_DIRECTIONPIS_DMA_BUFFER_SIZE'$PIS_DMA_PERIPHERAL_INC_STATEd PIS_DMA_MEMORY_INC_STATE$PIS_DMA_PERIPHERAL_DATA_SIZEj PIS_DMA_MEMORY_DATA_SIZEP IS_DMA_MODEdPIS_DMA_PRIORITYP__STM32F1xx_HAL_ETH_HPSTM32F1xx_HAL_CAN_HHAL_CAN_STATE_RESETHAL_CAN_STATE_READY HAL_CAN_STATE_LISTENING$HAL_CAN_STATE_SLEEP_PENDING#HAL_CAN_STATE_SLEEP_ACTIVEHAL_CAN_STATE_ERRORHAL_CAN_StateTypeDef8 Q "[ Prescaler "[Mode "[SyncJumpWidth: "[ TimeSeg1 "[ TimeSeg2 ""[TimeTriggeredMode ""[ AutoBusOff ""[ AutoWakeUp~ ""[AutoRetransmission ""[ReceiveFifoLocked ""[TransmitFifoPriorityCAN_InitTypeDefm8 Q "[ FilterIdHigh "[ FilterIdLow% "[FilterMaskIdHighA "[FilterMaskIdLow "[FilterFIFOAssignment "[ FilterBank "[ FilterMode "[ FilterScale "[FilterActivation "[SlaveStartFilterBankmCAN_FilterTypeDef8 Q "[StdId "[ExtId "[IDE "[RTRv "[DLC ""[TransmitGlobalTime CAN_TxHeaderTypeDef8 Q "\StdId  "\ExtId "\IDE "\RTR "\DLC "\ Timestamp% "\FilterMatchIndexCAN_RxHeaderTypeDef8__CAN_HandleTypeDef "\ Instance "\Init ""\State "\ ErrorCodeKCAN_HandleTypeDefPHAL_CAN_ERROR_NONE)PHAL_CAN_ERROR_EWGxPHAL_CAN_ERROR_EPVpPHAL_CAN_ERROR_BOFPHAL_CAN_ERROR_STFnPHAL_CAN_ERROR_FORtPHAL_CAN_ERROR_ACKPHAL_CAN_ERROR_BRPHAL_CAN_ERROR_BDPHAL_CAN_ERROR_CRCPHAL_CAN_ERROR_RX_FOV0/PHAL_CAN_ERROR_RX_FOV1.PHAL_CAN_ERROR_TX_ALST0PHAL_CAN_ERROR_TX_TERR0PHAL_CAN_ERROR_TX_ALST1PHAL_CAN_ERROR_TX_TERR1PHAL_CAN_ERROR_TX_ALST2PHAL_CAN_ERROR_TX_TERR2PHAL_CAN_ERROR_TIMEOUT,&PHAL_CAN_ERROR_NOT_INITIALIZED PHAL_CAN_ERROR_NOT_READY"PHAL_CAN_ERROR_NOT_STARTEDPHAL_CAN_ERROR_PARAMPHAL_CAN_ERROR_INTERNALPCAN_INITSTATUS_FAILEDTPCAN_INITSTATUS_SUCCESSPCAN_MODE_NORMAL/PCAN_MODE_LOOPBACKPCAN_MODE_SILENT)!PCAN_MODE_SILENT_LOOPBACKmP CAN_SJW_1TQ[P CAN_SJW_2TQZP CAN_SJW_3TQYP CAN_SJW_4TQXP CAN_BS1_1TQP CAN_BS1_2TQP CAN_BS1_3TQP CAN_BS1_4TQP CAN_BS1_5TQP CAN_BS1_6TQP CAN_BS1_7TQP CAN_BS1_8TQP CAN_BS1_9TQP CAN_BS1_10TQWP CAN_BS1_11TQVP CAN_BS1_12TQUP CAN_BS1_13TQTP CAN_BS1_14TQSP CAN_BS1_15TQRP CAN_BS1_16TQQP CAN_BS2_1TQP CAN_BS2_2TQP CAN_BS2_3TQP CAN_BS2_4TQP CAN_BS2_5TQP CAN_BS2_6TQP CAN_BS2_7TQP CAN_BS2_8TQPCAN_FILTERMODE_IDMASKmPCAN_FILTERMODE_IDLIST]PCAN_FILTERSCALE_16BITPCAN_FILTERSCALE_32BITPCAN_FILTER_DISABLE]PCAN_FILTER_ENABLEPCAN_FILTER_FIFO0PCAN_FILTER_FIFO1P CAN_ID_STDP CAN_ID_EXTP CAN_RTR_DATAPCAN_RTR_REMOTE[P CAN_RX_FIFO0%P CAN_RX_FIFO1$PCAN_TX_MAILBOX05PCAN_TX_MAILBOX14PCAN_TX_MAILBOX23PCAN_FLAG_RQCP0PCAN_FLAG_TXOK0PCAN_FLAG_ALST0PCAN_FLAG_TERR0PCAN_FLAG_RQCP1PCAN_FLAG_TXOK1PCAN_FLAG_ALST1PCAN_FLAG_TERR1PCAN_FLAG_RQCP2PCAN_FLAG_TXOK2PCAN_FLAG_ALST2PCAN_FLAG_TERR2PCAN_FLAG_TME0PCAN_FLAG_TME1PCAN_FLAG_TME2PCAN_FLAG_LOW0PCAN_FLAG_LOW1PCAN_FLAG_LOW2P CAN_FLAG_FF0MPCAN_FLAG_FOV0P CAN_FLAG_FF1LPCAN_FLAG_FOV1PCAN_FLAG_INAKPCAN_FLAG_SLAKPCAN_FLAG_ERRIP CAN_FLAG_WKUPCAN_FLAG_SLAKIP CAN_FLAG_EWG&P CAN_FLAG_EPVP CAN_FLAG_BOF2 PCAN_IT_TX_MAILBOX_EMPTYk$PCAN_IT_RX_FIFO0_MSG_PENDINGaPCAN_IT_RX_FIFO0_FULL PCAN_IT_RX_FIFO0_OVERRUN$PCAN_IT_RX_FIFO1_MSG_PENDING`PCAN_IT_RX_FIFO1_FULL PCAN_IT_RX_FIFO1_OVERRUNPCAN_IT_WAKEUPPCAN_IT_SLEEP_ACKPCAN_IT_ERROR_WARNINGwPCAN_IT_ERROR_PASSIVErPCAN_IT_BUSOFFPCAN_IT_LAST_ERROR_CODEP CAN_IT_ERROR%P__HAL_CAN_RESET_HANDLE_STATEP__HAL_CAN_ENABLE_ITP__HAL_CAN_DISABLE_IT P__HAL_CAN_GET_IT_SOURCEnP__HAL_CAN_GET_FLAG+P__HAL_CAN_CLEAR_FLAG ,hcan/ HAL_CAN_Init ,hcan/HAL_CAN_DeInit* ,hcan/HAL_CAN_MspInit ,hcan/HAL_CAN_MspDeInit ,hcan/,sFilterConfigHAL_CAN_ConfigFilter ,hcan/HAL_CAN_Start[ ,hcan/ HAL_CAN_Stop ,hcan/HAL_CAN_RequestSleepy ,hcan/HAL_CAN_WakeUp ,hcan/HAL_CAN_IsSleepActiveH ,hcan/,pHeader ,aData, pTxMailboxHAL_CAN_AddTxMessage ,hcan/,  TxMailboxesYHAL_CAN_AbortTxRequest ,hcan/( HAL_CAN_GetTxMailboxesFreeLevel; ,hcan/,  TxMailboxesY#HAL_CAN_IsTxMessagePending= ,hcan/,  TxMailbox5HAL_CAN_GetTxTimestamp ,hcan/, RxFifo,pHeader ,aDataHAL_CAN_GetRxMessage ,hcan/, RxFifo#HAL_CAN_GetRxFifoFillLevelb ,hcan/,  ActiveITsa%HAL_CAN_ActivateNotification3 ,hcan/,  InactiveITs'HAL_CAN_DeactivateNotificationf ,hcan/HAL_CAN_IRQHandler ,hcan/+#HAL_CAN_TxMailbox0CompleteCallback1 ,hcan/+#HAL_CAN_TxMailbox1CompleteCallback0 ,hcan/+#HAL_CAN_TxMailbox2CompleteCallback/ ,hcan/( HAL_CAN_TxMailbox0AbortCallbackx ,hcan/( HAL_CAN_TxMailbox1AbortCallbackw ,hcan/( HAL_CAN_TxMailbox2AbortCallbackv ,hcan/*"HAL_CAN_RxFifo0MsgPendingCallback ,hcan/$HAL_CAN_RxFifo0FullCallback/ ,hcan/*"HAL_CAN_RxFifo1MsgPendingCallback ,hcan/$HAL_CAN_RxFifo1FullCallback. ,hcan/HAL_CAN_SleepCallbackS ,hcan/( HAL_CAN_WakeUpFromRxMsgCallbackf ,hcan/HAL_CAN_ErrorCallbackB ,hcan/HAL_CAN_GetStateB ,hcan/HAL_CAN_GetError9 ,hcan/HAL_CAN_ResetErrorRPCAN_FLAG_MASKP IS_CAN_MODEdP IS_CAN_SJWP IS_CAN_BS1P IS_CAN_BS2PIS_CAN_PRESCALER"PIS_CAN_FILTER_ID_HALFWORD"PIS_CAN_FILTER_BANK_SINGLE PIS_CAN_FILTER_MODE1PIS_CAN_FILTER_SCALE!PIS_CAN_FILTER_ACTIVATIONXPIS_CAN_FILTER_FIFO2PIS_CAN_TX_MAILBOXfPIS_CAN_TX_MAILBOX_LISTP IS_CAN_STDIDP IS_CAN_EXTID P IS_CAN_DLCPIS_CAN_IDTYPEP IS_CAN_RTRPIS_CAN_RX_FIFOVP IS_CAN_IT&PHAL_CAN_LEGACY_MODULE_ENABLEDP__STM32F1xx_HAL_CEC_H!P__STM32F1xx_HAL_CORTEX_HPNVIC_PRIORITYGROUP_0vPNVIC_PRIORITYGROUP_1uPNVIC_PRIORITYGROUP_2tPNVIC_PRIORITYGROUP_3sPNVIC_PRIORITYGROUP_4r$PSYSTICK_CLKSOURCE_HCLK_DIV8fPSYSTICK_CLKSOURCE_HCLK, PriorityGroupV%HAL_NVIC_SetPriorityGrouping ,"IRQnh, PreemptPriority,  SubPriority=HAL_NVIC_SetPriorityo ,"IRQnhHAL_NVIC_EnableIRQ ,"IRQnhHAL_NVIC_DisableIRQ_HAL_NVIC_SystemResetu,  TicksNumb=HAL_SYSTICK_Config%HAL_NVIC_GetPriorityGrouping ,"IRQnh, PriorityGroupV,pPreemptPriority, pSubPriorityHAL_NVIC_GetPriority{ ,"IRQnhHAL_NVIC_GetPendingIRQ( ,"IRQnhHAL_NVIC_SetPendingIRQ ,"IRQnh!HAL_NVIC_ClearPendingIRQ] ,"IRQnhHAL_NVIC_GetActive,  CLKSource$HAL_SYSTICK_CLKSourceConfigTHAL_SYSTICK_IRQHandlerUHAL_SYSTICK_CallbackPIS_NVIC_PRIORITY_GROUP$PIS_NVIC_PREEMPTION_PRIORITY'PIS_NVIC_SUB_PRIORITYNPIS_NVIC_DEVICE_IRQ"PIS_SYSTICK_CLK_SOURCEP__STM32F1xx_HAL_ADC_H!8 Q "^ DataAlignM "^ ScanConvMode  ""^ContinuousConvMode9 "^NbrOfConversion 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ADC_ANALOGWATCHDOG_SINGLE_INJECz+P#ADC_ANALOGWATCHDOG_SINGLE_REGINJEC#PADC_ANALOGWATCHDOG_ALL_REG%PADC_ANALOGWATCHDOG_ALL_INJECi(P ADC_ANALOGWATCHDOG_ALL_REGINJECPADC_REGULAR_GROUPPADC_INJECTED_GROUPN#PADC_REGULAR_INJECTED_GROUPPADC_AWD_EVENTPADC_AWD1_EVENTP ADC_IT_EOCP ADC_IT_JEOCqP ADC_IT_AWDPADC_FLAG_STRTPADC_FLAG_JSTRTxP ADC_FLAG_EOC<PADC_FLAG_JEOCP ADC_FLAG_AWD75P-ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE56P.ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES577P/ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES57P/ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES57P/ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES57P/ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES57P/ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES58P0ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5-P%ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2-P%ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2-P%ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1-P%ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1-P%ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0-P%ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT00P(ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS81P)ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS2P*ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS2P*ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS2P*ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS2P*ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS2P*ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS3P+ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELSr0P(ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS91P)ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS2P*ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS2P*ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS2P*ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS2P*ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS2P*ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS3P+ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELSsPADC_FLAG_POSTCONV_ALLMP__HAL_ADC_ENABLEP__HAL_ADC_DISABLEP__HAL_ADC_ENABLE_ITP__HAL_ADC_DISABLE_IT P__HAL_ADC_GET_IT_SOURCExP__HAL_ADC_GET_FLAG5P__HAL_ADC_CLEAR_FLAG%P__HAL_ADC_RESET_HANDLE_STATE PADC_IS_ENABLE&PADC_IS_SOFTWARE_START_REGULAR'PADC_IS_SOFTWARE_START_INJECTEDpPADC_STATE_CLR_SETvPADC_CLEAR_ERRORCODEPADC_SQR1_L_SHIFTP ADC_SMPR1P ADC_SMPR2P ADC_SQR3_RKiP ADC_SQR2_RKjP ADC_SQR1_RKkPADC_JSQR_JL_SHIFTpPADC_JSQR_RK_JLWPADC_CR2_CONTINUOUSC"PADC_CR1_DISCONTINUOUS_NUMPADC_CR1_SCAN_SET!PADC_CONVCYCLES_MAX_RANGEjPIS_ADC_DATA_ALIGNPIS_ADC_SCAN_MODEPIS_ADC_EXTTRIG_EDGEPIS_ADC_CHANNELPIS_ADC_SAMPLE_TIME5PIS_ADC_REGULAR_RANK$PIS_ADC_ANALOG_WATCHDOG_MODE PIS_ADC_CONVERSION_GROUPPIS_ADC_EVENT_TYPEdP IS_ADC_RANGE$PIS_ADC_REGULAR_NB_CONV&PIS_ADC_REGULAR_DISCONT_NUMBER!P__STM32F1xx_HAL_ADC_EX_H8 Q "_InjectedChannel "_ InjectedRank "_InjectedSamplingTimel "_InjectedOffset" "_InjectedNbrOfConversion3( ""_InjectedDiscontinuousConvMode} ""_AutoInjectedConv "_ExternalTrigInjecConv!ADC_InjectionConfTypeDef8 Q "_ModeADC_MultiModeTypeDefqPADC_INJECTED_RANK_1PADC_INJECTED_RANK_2PADC_INJECTED_RANK_3PADC_INJECTED_RANK_4,P$ADC_EXTERNALTRIGINJECCONV_EDGE_NONE#.P&ADC_EXTERNALTRIGINJECCONV_EDGE_RISING$PADC_EXTERNALTRIGCONV_T1_CC1$PADC_EXTERNALTRIGCONV_T1_CC2$PADC_EXTERNALTRIGCONV_T2_CC2%PADC_EXTERNALTRIGCONV_T3_TRGO$PADC_EXTERNALTRIGCONV_T4_CC4&PADC_EXTERNALTRIGCONV_EXT_IT11$PADC_EXTERNALTRIGCONV_T2_CC3$PADC_EXTERNALTRIGCONV_T3_CC1$PADC_EXTERNALTRIGCONV_T5_CC1$PADC_EXTERNALTRIGCONV_T5_CC3$PADC_EXTERNALTRIGCONV_T8_CC1$PADC_EXTERNALTRIGCONV_T1_CC3%PADC_EXTERNALTRIGCONV_T8_TRGOPADC_SOFTWARE_START(*P"ADC_EXTERNALTRIGINJECCONV_T2_TRGO)P!ADC_EXTERNALTRIGINJECCONV_T2_CC11)P!ADC_EXTERNALTRIGINJECCONV_T3_CC4-*P"ADC_EXTERNALTRIGINJECCONV_T4_TRGO+P#ADC_EXTERNALTRIGINJECCONV_EXT_IT15v)P!ADC_EXTERNALTRIGINJECCONV_T4_CC3-)P!ADC_EXTERNALTRIGINJECCONV_T8_CC2**P"ADC_EXTERNALTRIGINJECCONV_T5_TRGO)P!ADC_EXTERNALTRIGINJECCONV_T5_CC4+)P!ADC_EXTERNALTRIGINJECCONV_T1_CC4/*P"ADC_EXTERNALTRIGINJECCONV_T1_TRGO)P!ADC_EXTERNALTRIGINJECCONV_T8_CC4($PADC_INJECTED_SOFTWARE_STARTqPADC_MODE_INDEPENDENT+P#ADC_DUALMODE_REGSIMULT_INJECSIMULTT)P!ADC_DUALMODE_REGSIMULT_ALTERTRIG,P$ADC_DUALMODE_INJECSIMULT_INTERLFAST,P$ADC_DUALMODE_INJECSIMULT_INTERLSLOW!PADC_DUALMODE_INJECSIMULTPADC_DUALMODE_REGSIMULT PADC_DUALMODE_INTERLFAST PADC_DUALMODE_INTERLSLOWPADC_DUALMODE_ALTERTRIG #PADC1_2_EXTERNALTRIG_T1_CC1#PADC1_2_EXTERNALTRIG_T1_CC2#PADC1_2_EXTERNALTRIG_T2_CC2$PADC1_2_EXTERNALTRIG_T3_TRGO#PADC1_2_EXTERNALTRIG_T4_CC4%PADC1_2_EXTERNALTRIG_EXT_IT11c$PADC1_2_EXTERNALTRIG_T8_TRGO!PADC3_EXTERNALTRIG_T3_CC1!PADC3_EXTERNALTRIG_T2_CC3!PADC3_EXTERNALTRIG_T8_CC1"PADC3_EXTERNALTRIG_T8_TRGO !PADC3_EXTERNALTRIG_T5_CC1!PADC3_EXTERNALTRIG_T5_CC3%PADC1_2_3_EXTERNALTRIG_T1_CC3PADC1_2_3_SWSTART)P!ADC1_2_EXTERNALTRIGINJEC_T2_TRGO (P ADC1_2_EXTERNALTRIGINJEC_T2_CC1(P ADC1_2_EXTERNALTRIGINJEC_T3_CC4)P!ADC1_2_EXTERNALTRIGINJEC_T4_TRGO*P"ADC1_2_EXTERNALTRIGINJEC_EXT_IT15(P ADC1_2_EXTERNALTRIGINJEC_T8_CC4&PADC3_EXTERNALTRIGINJEC_T4_CC36&PADC3_EXTERNALTRIGINJEC_T8_CC23&PADC3_EXTERNALTRIGINJEC_T8_CC41'PADC3_EXTERNALTRIGINJEC_T5_TRGO&PADC3_EXTERNALTRIGINJEC_T5_CC44+P#ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO*P"ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4PADC1_2_3_JSWSTARTPADC_CFGR_EXTSEL0PADC_CFGR_JEXTSEL PADC_MULTIMODE_IS_ENABLE,P$ADC_NONMULTIMODE_OR_MULTIMODEMASTER$PADC_MULTIMODE_AUTO_INJECTEDPADC_COMMON_ADC_OTHERPADC_MULTI_SLAVE!PIS_ADC_INJECTED_RANK!PIS_ADC_EXTTRIGINJEC_EDGEu PIS_ADC_INJECTED_NB_CONVPIS_ADC_EXTTRIGfPIS_ADC_EXTTRIGINJECP IS_ADC_MODEn ,hadc9$HAL_ADCEx_Calibration_Start ,hadc9 HAL_ADCEx_InjectedStartn ,hadc9HAL_ADCEx_InjectedStop ,hadc9, Timeout,$HAL_ADCEx_InjectedPollForConversion ,hadc9#HAL_ADCEx_InjectedStart_ITl ,hadc9"HAL_ADCEx_InjectedStop_IT ,hadc9,pData, Lengthq%HAL_ADCEx_MultiModeStart_DMA ,hadc9$HAL_ADCEx_MultiModeStop_DMA3 ,hadc9,  InjectedRank#HAL_ADCEx_InjectedGetValueY ,hadc9$HAL_ADCEx_MultiModeGetValue ,hadc9+#HAL_ADCEx_InjectedConvCpltCallback0 ,hadc9,sConfigInjected( HAL_ADCEx_InjectedConfigChannel] ,hadc9, multimode)!HAL_ADCEx_MultiModeConfigChannel ,hadc9 HAL_ADC_Init ,hadc9HAL_ADC_DeInit4 ,hadc9HAL_ADC_MspInit ,hadc9HAL_ADC_MspDeInit ,hadc9HAL_ADC_Starte ,hadc9 HAL_ADC_Stop ,hadc9, Timeout"HAL_ADC_PollForConversionw ,hadc9,  EventType), TimeoutHAL_ADC_PollForEvent ,hadc9HAL_ADC_Start_ITc ,hadc9HAL_ADC_Stop_IT ,hadc9,pData, LengthqHAL_ADC_Start_DMA, ,hadc9HAL_ADC_Stop_DMA ,hadc9HAL_ADC_GetValueP ,hadc9HAL_ADC_IRQHandler ,hadc9!HAL_ADC_ConvCpltCallback' ,hadc9%HAL_ADC_ConvHalfCpltCallback ,hadc9)!HAL_ADC_LevelOutOfWindowCallback ,hadc9HAL_ADC_ErrorCallbackL ,hadc9,sConfigHAL_ADC_ConfigChannelT ,hadc9,AnalogWDGConfig) HAL_ADC_AnalogWDGConfig ,hadc9HAL_ADC_GetStateL ,hadc9HAL_ADC_GetErrorC ,hadc9 ADC_Enablef ,hadc9#ADC_ConversionStop_Disable, DelayUsADC_StabilizationTime ,hdma/ADC_DMAConvCplt ,hdma/ADC_DMAHalfConvCplt% ,hdma/ ADC_DMAErrorPSTM32F1xx_HAL_CRC_HHAL_CRC_STATE_RESET HAL_CRC_STATE_READYHAL_CRC_STATE_BUSYKHAL_CRC_STATE_TIMEOUTaHAL_CRC_STATE_ERRORHAL_CRC_StateTypeDef8 Q "a Instanceg ""aLock ""aStateCRC_HandleTypeDef%P__HAL_CRC_RESET_HANDLE_STATEP__HAL_CRC_DR_RESETP__HAL_CRC_SET_IDRVP__HAL_CRC_GET_IDRb ,hcrc) HAL_CRC_Init ,hcrc)HAL_CRC_DeInit$ ,hcrc)HAL_CRC_MspInit ,hcrc)HAL_CRC_MspDeInit ,hcrc),pBuffer,  BufferLength HAL_CRC_AccumulateU ,hcrc),pBuffer,  BufferLength HAL_CRC_Calculate ,hcrc)HAL_CRC_GetState<PSTM32F1xx_HAL_DAC_HHAL_DAC_STATE_RESETHAL_DAC_STATE_READY'HAL_DAC_STATE_BUSY[HAL_DAC_STATE_TIMEOUTqHAL_DAC_STATE_ERRORHAL_DAC_StateTypeDef8 Q "a InstanceE ""aStatex ""aLock "a DMA_Handle1 "a DMA_Handle2 "a ErrorCodeDAC_HandleTypeDef8 Q "a DAC_Trigger "aDAC_OutputBuffer^DAC_ChannelConfTypeDefPHAL_DAC_ERROR_NONE3%PHAL_DAC_ERROR_DMAUNDERRUNCH1N%PHAL_DAC_ERROR_DMAUNDERRUNCH2MPHAL_DAC_ERROR_DMAPHAL_DAC_ERROR_TIMEOUT6 PDAC_OUTPUTBUFFER_ENABLE!PDAC_OUTPUTBUFFER_DISABLEvPDAC_CHANNEL_1PDAC_CHANNEL_2PDAC_ALIGN_12B_RfPDAC_ALIGN_12B_LlPDAC_ALIGN_8B_RPDAC_FLAG_DMAUDR1PDAC_FLAG_DMAUDR2PDAC_IT_DMAUDR1PDAC_IT_DMAUDR2%P__HAL_DAC_RESET_HANDLE_STATE P__HAL_DAC_ENABLEP__HAL_DAC_DISABLEPDAC_DHR12R1_ALIGNMENTPDAC_DHR12R2_ALIGNMENTPDAC_DHR12RD_ALIGNMENTP__HAL_DAC_ENABLE_ITP__HAL_DAC_DISABLE_IT P__HAL_DAC_GET_IT_SOURCExP__HAL_DAC_GET_FLAG5P__HAL_DAC_CLEAR_FLAG#PIS_DAC_OUTPUT_BUFFER_STATEPIS_DAC_CHANNELP IS_DAC_ALIGN&P IS_DAC_DATAyPSTM32F1xx_HAL_DAC_EX_HPDAC_LFSRUNMASK_BIT0 PDAC_LFSRUNMASK_BITS1_0!PDAC_LFSRUNMASK_BITS2_0 PDAC_LFSRUNMASK_BITS3_0PDAC_LFSRUNMASK_BITS4_0PDAC_LFSRUNMASK_BITS5_0PDAC_LFSRUNMASK_BITS6_0PDAC_LFSRUNMASK_BITS7_0PDAC_LFSRUNMASK_BITS8_0PDAC_LFSRUNMASK_BITS9_0 PDAC_LFSRUNMASK_BITS10_0 PDAC_LFSRUNMASK_BITS11_0 PDAC_TRIANGLEAMPLITUDE_1 PDAC_TRIANGLEAMPLITUDE_3 PDAC_TRIANGLEAMPLITUDE_7!PDAC_TRIANGLEAMPLITUDE_15!PDAC_TRIANGLEAMPLITUDE_31!PDAC_TRIANGLEAMPLITUDE_63"PDAC_TRIANGLEAMPLITUDE_127~"PDAC_TRIANGLEAMPLITUDE_255|"PDAC_TRIANGLEAMPLITUDE_511#PDAC_TRIANGLEAMPLITUDE_1023P#PDAC_TRIANGLEAMPLITUDE_2047I#PDAC_TRIANGLEAMPLITUDE_4095DPDAC_TRIGGER_NONEPDAC_TRIGGER_T6_TRGOPDAC_TRIGGER_T7_TRGOPDAC_TRIGGER_T2_TRGOPDAC_TRIGGER_T4_TRGOPDAC_TRIGGER_EXT_IT9PDAC_TRIGGER_SOFTWAREPDAC_TRIGGER_T8_TRGOPDAC_TRIGGER_T5_TRGOPIS_DAC_TRIGGERy.P&IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDEA ,hdac9, Channel,  Amplitude('HAL_DACEx_TriangleWaveGenerate ,hdac9, Channel,  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,hdma/DAC_DMAHalfConvCpltCh1C P__STM32F1xx_HAL_FLASH_HwPFLASH_TIMEOUT_VALUEPIS_FLASH_TYPEPROGRAMPIS_FLASH_LATENCYFLASH_PROC_NONEOFLASH_PROC_PAGEERASEFLASH_PROC_MASSERASE#FLASH_PROC_PROGRAMHALFWORDFLASH_PROC_PROGRAMWORD%FLASH_PROC_PROGRAMDOUBLEWORDVFLASH_ProcedureTypeDef8 Q ""bProcedureOnGoing "bDataRemaining; "bAddress ("bData ""bLock "b ErrorCodeFLASH_ProcessTypeDef|PHAL_FLASH_ERROR_NONEPHAL_FLASH_ERROR_PROGPHAL_FLASH_ERROR_WRPPHAL_FLASH_ERROR_OPTVp#PFLASH_TYPEPROGRAM_HALFWORDPFLASH_TYPEPROGRAM_WORD%PFLASH_TYPEPROGRAM_DOUBLEWORDPFLASH_LATENCY_0APFLASH_LATENCY_1@PFLASH_LATENCY_2?-P%__HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE.P&__HAL_FLASH_HALF_CYCLE_ACCESS_DISABLEt P__HAL_FLASH_SET_LATENCY P__HAL_FLASH_GET_LATENCY+P#__HAL_FLASH_PREFETCH_BUFFER_ENABLEX,P$__HAL_FLASH_PREFETCH_BUFFER_DISABLE #P__STM32F1xx_HAL_FLASH_EX_Hu!PFLASH_SIZE_DATA_REGISTERVPOBR_REG_INDEXP SR_FLAG_MASK PIS_FLASH_TYPEERASE-PIS_OPTIONBYTEP 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FLASH_BANK_1:POPTIONBYTE_WRPJPOPTIONBYTE_RDP]POPTIONBYTE_USERPOPTIONBYTE_DATA'POB_WRPSTATE_DISABLEPOB_WRPSTATE_ENABLE7POB_WRP_PAGES0TO1POB_WRP_PAGES2TO3POB_WRP_PAGES4TO5POB_WRP_PAGES6TO7POB_WRP_PAGES8TO9POB_WRP_PAGES10TO11POB_WRP_PAGES12TO13POB_WRP_PAGES14TO15POB_WRP_PAGES16TO17}POB_WRP_PAGES18TO19yPOB_WRP_PAGES20TO21POB_WRP_PAGES22TO23POB_WRP_PAGES24TO25POB_WRP_PAGES26TO27{POB_WRP_PAGES28TO29wPOB_WRP_PAGES30TO31POB_WRP_PAGES32TO33POB_WRP_PAGES34TO35}POB_WRP_PAGES36TO37yPOB_WRP_PAGES38TO39uPOB_WRP_PAGES40TO41POB_WRP_PAGES42TO43POB_WRP_PAGES44TO45{POB_WRP_PAGES46TO47wPOB_WRP_PAGES48TO49sPOB_WRP_PAGES50TO51POB_WRP_PAGES52TO53}POB_WRP_PAGES54TO55yPOB_WRP_PAGES56TO57uPOB_WRP_PAGES58TO59qPOB_WRP_PAGES60TO61POB_WRP_PAGES62TO127HPOB_WRP_PAGES62TO255FPOB_WRP_PAGES62TO511KPOB_WRP_ALLPAGESPOB_WRP_PAGES0TO15MASKPOB_WRP_PAGES16TO31MASKMPOB_WRP_PAGES32TO47MASKH POB_WRP_PAGES48TO255MASKPOB_RDP_LEVEL_0sPOB_RDP_LEVEL_1rP OB_IWDG_SWP OB_IWDG_HWPOB_STOP_NO_RST%P OB_STOP_RST'POB_STDBY_NO_RSTP OB_STDBY_RSTPOB_DATA_ADDRESS_DATA0POB_DATA_ADDRESS_DATA1PFLASH_FLAG_BSY{PFLASH_FLAG_PGERRPFLASH_FLAG_WRPERRPFLASH_FLAG_EOPPFLASH_FLAG_OPTVERR/P FLASH_IT_EOPP FLASH_IT_ERRP__HAL_FLASH_ENABLE_IT?P__HAL_FLASH_DISABLE_ITP__HAL_FLASH_GET_FLAGP__HAL_FLASH_CLEAR_FLAG, pEraseInit, PageError8HAL_FLASHEx_Erase, pEraseInitHAL_FLASHEx_Erase_ITHAL_FLASHEx_OBErase,pOBInit.HAL_FLASHEx_OBProgram,pOBInit. HAL_FLASHEx_OBGetConfig,  DATAAdressO"HAL_FLASHEx_OBGetUserData.,  TypeProgramO, Address ,(Data;HAL_FLASH_Program,  TypeProgramO, Address ,(Data;HAL_FLASH_Program_ITHAL_FLASH_IRQHandler,  ReturnValueL)!HAL_FLASH_EndOfOperationCallback,  ReturnValueL)!HAL_FLASH_OperationErrorCallbackHAL_FLASH_Unlock[HAL_FLASH_LockBHAL_FLASH_OB_UnlockeHAL_FLASH_OB_LockLHAL_FLASH_OB_LaunchvHAL_FLASH_GetError, Timeout#FLASH_WaitForLastOperationPSTM32F1xx_HAL_SRAM_HvPSTM32F1xx_LL_FSMC_HPIS_FSMC_NORSRAM_BANKP IS_FSMC_MUX8PIS_FSMC_MEMORYS%PIS_FSMC_NORSRAM_MEMORY_WIDTHPIS_FSMC_PAGESIZEPIS_FSMC_ACCESS_MODEPIS_FSMC_BURSTMODEqPIS_FSMC_WAIT_POLARITYPIS_FSMC_WRAP_MODEh#PIS_FSMC_WAIT_SIGNAL_ACTIVE PIS_FSMC_WRITE_OPERATIONPIS_FSMC_WAITE_SIGNALPIS_FSMC_EXTENDED_MODEIPIS_FSMC_ASYNWAITPIS_FSMC_DATA_LATENCYPIS_FSMC_WRITE_BURST PIS_FSMC_CONTINOUS_CLOCK#PIS_FSMC_ADDRESS_SETUP_TIME"PIS_FSMC_ADDRESS_HOLD_TIMEPIS_FSMC_DATASETUP_TIME"PIS_FSMC_DATAHOLD_DURATION PIS_FSMC_TURNAROUND_TIMEzPIS_FSMC_CLK_DIVPIS_FSMC_NORSRAM_DEVICE(P IS_FSMC_NORSRAM_EXTENDED_DEVICE)PIS_FSMC_NAND_BANKPIS_FSMC_WAIT_FEATURE"PIS_FSMC_NAND_MEMORY_WIDTHPIS_FSMC_ECC_STATE{PIS_FSMC_ECCPAGE_SIZEPIS_FSMC_TCLR_TIMEcPIS_FSMC_TAR_TIMEPIS_FSMC_SETUP_TIMEPIS_FSMC_WAIT_TIMEcPIS_FSMC_HOLD_TIMEqPIS_FSMC_HIZ_TIMEPIS_FSMC_NAND_DEVICEPIS_FSMC_PCCARD_DEVICEbPFSMC_NORSRAM_TypeDef&PFSMC_NORSRAM_EXTENDED_TypeDef'PFSMC_NAND_TypeDefPFSMC_PCCARD_TypeDef`PFSMC_NORSRAM_DEVICE%PFSMC_NORSRAM_EXTENDED_DEVICE*PFSMC_NAND_DEVICEPFSMC_PCCARD_DEVICEc8 Q "dNSBanko "dDataAddressMux "d MemoryTypei "dMemoryDataWidth "dBurstAccessMode "dWaitSignalPolarity- "d WrapModei "dWaitSignalActive) "dWriteOperation "d WaitSignal "d ExtendedMode "dAsynchronousWait "d WriteBursti "d PageSizep!FSMC_NORSRAM_InitTypeDef8 Q "dAddressSetupTime "dAddressHoldTime "dDataSetupTimeT "dBusTurnAroundDuration "d CLKDivisionS "d DataLatency( "d AccessMode#FSMC_NORSRAM_TimingTypeDef8 Q "d NandBankr "d Waitfeature "dMemoryDataWidthn "dEccComputation "d ECCPageSize "dTCLRSetupTime "d TARSetupTimeFSMC_NAND_InitTypeDef8 Q "d SetupTime "dWaitSetupTime' "dHoldSetupTime5 "d HiZSetupTime$FSMC_NAND_PCC_TimingTypeDefu8 Q "d Waitfeature "dTCLRSetupTime "d TARSetupTime FSMC_PCCARD_InitTypeDefPFSMC_NORSRAM_BANK1QPFSMC_NORSRAM_BANK2PPFSMC_NORSRAM_BANK3OPFSMC_NORSRAM_BANK4N&PFSMC_DATA_ADDRESS_MUX_DISABLE%PFSMC_DATA_ADDRESS_MUX_ENABLE-PFSMC_MEMORY_TYPE_SRAM PFSMC_MEMORY_TYPE_PSRAMPFSMC_MEMORY_TYPE_NORS%PFSMC_NORSRAM_MEM_BUS_WIDTH_8&PFSMC_NORSRAM_MEM_BUS_WIDTH_16&PFSMC_NORSRAM_MEM_BUS_WIDTH_32)P!FSMC_NORSRAM_FLASH_ACCESS_ENABLE*P"FSMC_NORSRAM_FLASH_ACCESS_DISABLE'PFSMC_BURST_ACCESS_MODE_DISABLE&PFSMC_BURST_ACCESS_MODE_ENABLE&PFSMC_WAIT_SIGNAL_POLARITY_LOW'PFSMC_WAIT_SIGNAL_POLARITY_HIGHcPFSMC_WRAP_MODE_DISABLEPFSMC_WRAP_MODE_ENABLEU#PFSMC_WAIT_TIMING_BEFORE_WS#PFSMC_WAIT_TIMING_DURING_WS%PFSMC_WRITE_OPERATION_DISABLE$PFSMC_WRITE_OPERATION_ENABLEl!PFSMC_WAIT_SIGNAL_DISABLEn PFSMC_WAIT_SIGNAL_ENABLE#PFSMC_EXTENDED_MODE_DISABLE"PFSMC_EXTENDED_MODE_ENABLE6'PFSMC_ASYNCHRONOUS_WAIT_DISABLEt&PFSMC_ASYNCHRONOUS_WAIT_ENABLEPFSMC_PAGE_SIZE_NONEPFSMC_PAGE_SIZE_128nPFSMC_PAGE_SIZE_256lPFSMC_PAGE_SIZE_512qPFSMC_PAGE_SIZE_1024@!PFSMC_WRITE_BURST_DISABLEF PFSMC_WRITE_BURST_ENABLE(P FSMC_CONTINUOUS_CLOCK_SYNC_ONLY)P!FSMC_CONTINUOUS_CLOCK_SYNC_ASYNCPFSMC_ACCESS_MODE_AIPFSMC_ACCESS_MODE_BHPFSMC_ACCESS_MODE_CGPFSMC_ACCESS_MODE_DFPFSMC_NAND_BANK2WPFSMC_NAND_BANK3V+P#FSMC_NAND_PCC_WAIT_FEATURE_DISABLEW*P"FSMC_NAND_PCC_WAIT_FEATURE_ENABLE$PFSMC_PCR_MEMORY_TYPE_PCCARDC"PFSMC_PCR_MEMORY_TYPE_NAND&PFSMC_NAND_PCC_MEM_BUS_WIDTH_8'PFSMC_NAND_PCC_MEM_BUS_WIDTH_16PFSMC_NAND_ECC_DISABLE{PFSMC_NAND_ECC_ENABLE(P FSMC_NAND_ECC_PAGE_SIZE_256BYTEt(P FSMC_NAND_ECC_PAGE_SIZE_512BYTEy)P!FSMC_NAND_ECC_PAGE_SIZE_1024BYTEH)P!FSMC_NAND_ECC_PAGE_SIZE_2048BYTEA)P!FSMC_NAND_ECC_PAGE_SIZE_4096BYTE<)P!FSMC_NAND_ECC_PAGE_SIZE_8192BYTE;PFSMC_IT_RISING_EDGEPFSMC_IT_LEVELPFSMC_IT_FALLING_EDGEPFSMC_FLAG_RISING_EDGE`PFSMC_FLAG_LEVEL4PFSMC_FLAG_FALLING_EDGE-PFSMC_FLAG_FEMPT0P__FSMC_NORSRAM_ENABLE3P__FSMC_NORSRAM_DISABLEP__FSMC_NAND_ENABLE:P__FSMC_NAND_DISABLEP__FSMC_PCCARD_ENABLEP__FSMC_PCCARD_DISABLE[P__FSMC_NAND_ENABLE_IT8P__FSMC_NAND_DISABLE_ITP__FSMC_NAND_GET_FLAGP__FSMC_NAND_CLEAR_FLAG P__FSMC_PCCARD_ENABLE_IT!P__FSMC_PCCARD_DISABLE_ITYP__FSMC_PCCARD_GET_FLAG!P__FSMC_PCCARD_CLEAR_FLAGi,Deviceu ,Init5FSMC_NORSRAM_Init),Deviceu,Timing] , Bank[!FSMC_NORSRAM_Timing_InitT,Deviceu,Timing] , Bank[,  ExtendedMode*"FSMC_NORSRAM_Extended_Timing_Init,Deviceu, ExDevice , Bank[FSMC_NORSRAM_DeInit|,Deviceu , Bank[+#FSMC_NORSRAM_WriteOperation_Enable9,Deviceu , Bank[,$FSMC_NORSRAM_WriteOperation_Disable,Deviceu ,Init5FSMC_NAND_Init0,Deviceu,Timing] , Bank[*"FSMC_NAND_CommonSpace_Timing_Init,Deviceu,Timing] , Bank[-%FSMC_NAND_AttributeSpace_Timing_Init>,Deviceu , Bank[FSMC_NAND_DeInit,Deviceu , Bank[FSMC_NAND_ECC_EnableG,Deviceu , Bank[FSMC_NAND_ECC_Disable,Deviceu,ECCval , Bank[, TimeoutFSMC_NAND_GetECC,Deviceu ,Init5FSMC_PCCARD_Init,Deviceu,Timing],$FSMC_PCCARD_CommonSpace_Timing_Init,Deviceu,Timing]/'FSMC_PCCARD_AttributeSpace_Timing_Init,Deviceu,Timing]( FSMC_PCCARD_IOSpace_Timing_Init,DeviceuFSMC_PCCARD_DeInitHAL_SRAM_STATE_RESETHAL_SRAM_STATE_READYHAL_SRAM_STATE_BUSYHAL_SRAM_STATE_ERROR!HAL_SRAM_STATE_PROTECTED}HAL_SRAM_StateTypeDef_8 Q "f Instance "f Extended "8fInit ""fLock0 ""fState "fhdma&SRAM_HandleTypeDefN&P__HAL_SRAM_RESET_HANDLE_STATE,hsram,Timing], ExtTiming&HAL_SRAM_Initt,hsramHAL_SRAM_DeInit,hsramHAL_SRAM_MspInit>,hsramHAL_SRAM_MspDeInit,hsram, pAddress, pDstBuffer,  BufferSizeHAL_SRAM_Read_8b,hsram, pAddress, pSrcBuffer,  BufferSizeHAL_SRAM_Write_8b,hsram, pAddress, pDstBuffer,  BufferSizeHAL_SRAM_Read_16b\,hsram, pAddress, pSrcBuffer,  BufferSizeHAL_SRAM_Write_16b,hsram, pAddress, pDstBuffer,  BufferSizeHAL_SRAM_Read_32b^,hsram, pAddress, pSrcBuffer,  BufferSizeHAL_SRAM_Write_32b,hsram, pAddress, pDstBuffer,  BufferSizeHAL_SRAM_Read_DMAS,hsram, pAddress, pSrcBuffer,  BufferSizeHAL_SRAM_Write_DMA ,hdma/&HAL_SRAM_DMA_XferCpltCallback ,hdma/'HAL_SRAM_DMA_XferErrorCallback ,hsram'HAL_SRAM_WriteOperation_Enable,hsram( HAL_SRAM_WriteOperation_Disable,hsramHAL_SRAM_GetStatePSTM32F1xx_HAL_NOR_HHAL_NOR_STATE_RESETHAL_NOR_STATE_READYHAL_NOR_STATE_BUSY4HAL_NOR_STATE_ERROR HAL_NOR_STATE_PROTECTEDHAL_NOR_StateTypeDefHAL_NOR_STATUS_SUCCESSHAL_NOR_STATUS_ONGOINGHAL_NOR_STATUS_ERRORHAL_NOR_STATUS_TIMEOUTHAL_NOR_StatusTypeDef 8 Q "fManufacturer_Code "f Device_Code1 "f Device_Code2 "f Device_Code3NOR_IDTypeDef[8 Q "fCFI_1 "fCFI_2 "fCFI_3 "fCFI_4NOR_CFITypeDef8 Q "f Instance& "f Extended* "8fInit ""fLock ""fStateYNOR_HandleTypeDef%P__HAL_NOR_RESET_HANDLE_STATE ,hnor,Timing], ExtTiming& HAL_NOR_Init ,hnorHAL_NOR_DeInit ,hnorHAL_NOR_MspInit ,hnorHAL_NOR_MspDeInit ,hnor, TimeoutHAL_NOR_MspWait ,hnor,pNOR_IDxHAL_NOR_Read_ID ,hnor!HAL_NOR_ReturnToReadMode ,hnor, pAddress,pData HAL_NOR_Read ,hnor, pAddress,pDataHAL_NOR_Programp ,hnor,  uwAddress,pData,  uwBufferSizeHAL_NOR_ReadBufferl ,hnor,  uwAddress,pData,  uwBufferSizeHAL_NOR_ProgramBuffer ,hnor,  BlockAddress, Address HAL_NOR_Erase_Block ,hnor, Address HAL_NOR_Erase_Chipo ,hnor, pNOR_CFI1HAL_NOR_Read_CFI ,hnor&HAL_NOR_WriteOperation_Enable ,hnor'HAL_NOR_WriteOperation_Disable[ ,hnorHAL_NOR_GetState% ,hnor, Address , TimeoutHAL_NOR_GetStatusP MC_ADDRESSPDEVICE_CODE1_ADDRPDEVICE_CODE2_ADDRPDEVICE_CODE3_ADDRP CFI1_ADDRESSKP CFI2_ADDRESSJP CFI3_ADDRESSIP CFI4_ADDRESSHP NOR_TMEOUTPNOR_MEMORY_8BPNOR_MEMORY_16BPNOR_MEMORY_ADRESS1.PNOR_MEMORY_ADRESS2-PNOR_MEMORY_ADRESS3,PNOR_MEMORY_ADRESS4+PNOR_ADDR_SHIFTiP NOR_WRITEP__STM32F1xx_HAL_I2C_H+8 Q "g ClockSpeed "g DutyCycle "g OwnAddress1e "gAddressingMode "gDualAddressMode "g OwnAddress2d "gGeneralCallMode "gNoStretchModemI2C_InitTypeDefHAL_I2C_STATE_RESET#HAL_I2C_STATE_READY1HAL_I2C_STATE_BUSYeHAL_I2C_STATE_BUSY_TXTHAL_I2C_STATE_BUSY_RXVHAL_I2C_STATE_LISTEN%HAL_I2C_STATE_BUSY_TX_LISTEN%HAL_I2C_STATE_BUSY_RX_LISTENHAL_I2C_STATE_ABORT.HAL_I2C_STATE_TIMEOUT{HAL_I2C_STATE_ERRORHAL_I2C_StateTypeDefHAL_I2C_MODE_NONEHAL_I2C_MODE_MASTER6HAL_I2C_MODE_SLAVEHAL_I2C_MODE_MEM)HAL_I2C_ModeTypeDefTPHAL_I2C_ERROR_NONE=PHAL_I2C_ERROR_BERRBPHAL_I2C_ERROR_ARLO?PHAL_I2C_ERROR_AFPHAL_I2C_ERROR_OVRxPHAL_I2C_ERROR_DMAPHAL_I2C_ERROR_TIMEOUT@PHAL_I2C_ERROR_SIZE2 PHAL_I2C_ERROR_DMA_PARAM8__I2C_HandleTypeDef "g Instance/ " gInit "g pBuffPtr; "g XferSize@ "g XferCount "g XferOptions "gPreviousState  "ghdmatx "ghdmarx ""gLock ""gStateb ""gMode "g ErrorCode "g Devaddressi "g Memaddressi "g MemaddSize "g EventCountcI2C_HandleTypeDefPI2C_DUTYCYCLE_2IPI2C_DUTYCYCLE_16_9v PI2C_ADDRESSINGMODE_7BIT!PI2C_ADDRESSINGMODE_10BIT PI2C_DUALADDRESS_DISABLEPI2C_DUALADDRESS_ENABLEP PI2C_GENERALCALL_DISABLEPI2C_GENERALCALL_ENABLEbPI2C_NOSTRETCH_DISABLEwPI2C_NOSTRETCH_ENABLEPI2C_MEMADD_SIZE_8BITPI2C_MEMADD_SIZE_16BITPI2C_DIRECTION_RECEIVEPI2C_DIRECTION_TRANSMITPI2C_FIRST_FRAME>!PI2C_FIRST_AND_NEXT_FRAME\PI2C_NEXT_FRAME!PI2C_FIRST_AND_LAST_FRAMEgPI2C_LAST_FRAME_NO_STOPPI2C_LAST_FRAMEPI2C_OTHER_FRAMED!PI2C_OTHER_AND_LAST_FRAMEmP I2C_IT_BUFP I2C_IT_EVTP I2C_IT_ERRP I2C_FLAG_OVR&P I2C_FLAG_AFPI2C_FLAG_ARLOPI2C_FLAG_BERRP I2C_FLAG_TXE,PI2C_FLAG_RXNEPI2C_FLAG_STOPFPI2C_FLAG_ADD10P I2C_FLAG_BTFAPI2C_FLAG_ADDRP I2C_FLAG_SBPI2C_FLAG_DUALFPI2C_FLAG_GENCALLP I2C_FLAG_TRA6PI2C_FLAG_BUSYP I2C_FLAG_MSL1%P__HAL_I2C_RESET_HANDLE_STATEP__HAL_I2C_ENABLE_ITP__HAL_I2C_DISABLE_IT P__HAL_I2C_GET_IT_SOURCEP__HAL_I2C_GET_FLAG?P__HAL_I2C_CLEAR_FLAG!P__HAL_I2C_CLEAR_ADDRFLAG!P__HAL_I2C_CLEAR_STOPFLAGfP__HAL_I2C_ENABLEP__HAL_I2C_DISABLE ,hi2cc HAL_I2C_Init ,hi2ccHAL_I2C_DeInit> ,hi2ccHAL_I2C_MspInit ,hi2ccHAL_I2C_MspDeInit ,hi2cc, DevAddress,pData ,Size:, Timeout HAL_I2C_Master_TransmitL ,hi2cc, DevAddress,pData ,Size:, TimeoutHAL_I2C_Master_Receive ,hi2cc,pData ,Size:, TimeoutHAL_I2C_Slave_Transmit ,hi2cc,pData ,Size:, TimeoutHAL_I2C_Slave_ReceiveP ,hi2cc, DevAddress, MemAddress, MemAddSize,pData ,Size:, TimeoutHAL_I2C_Mem_Write ,hi2cc, DevAddress, MemAddress, MemAddSize,pData ,Size:, TimeoutHAL_I2C_Mem_Read} ,hi2cc, DevAddress, Trialsd, TimeoutHAL_I2C_IsDeviceReadyl ,hi2cc, DevAddress,pData ,Size:#HAL_I2C_Master_Transmit_ITJ ,hi2cc, DevAddress,pData ,Size:"HAL_I2C_Master_Receive_IT ,hi2cc,pData ,Size:"HAL_I2C_Slave_Transmit_IT ,hi2cc,pData ,Size:!HAL_I2C_Slave_Receive_ITN ,hi2cc, DevAddress, MemAddress, MemAddSize,pData ,Size:HAL_I2C_Mem_Write_IT ,hi2cc, DevAddress, MemAddress, MemAddSize,pData ,Size:HAL_I2C_Mem_Read_IT{ ,hi2cc, DevAddress,pData ,Size:,  XferOptionsH'HAL_I2C_Master_Seq_Transmit_IT ,hi2cc, DevAddress,pData ,Size:,  XferOptionsH&HAL_I2C_Master_Seq_Receive_ITK ,hi2cc,pData ,Size:,  XferOptionsH&HAL_I2C_Slave_Seq_Transmit_IT- ,hi2cc,pData ,Size:,  XferOptionsH%HAL_I2C_Slave_Seq_Receive_IT ,hi2cc HAL_I2C_EnableListen_IT ,hi2cc!HAL_I2C_DisableListen_ITH ,hi2cc, DevAddress HAL_I2C_Master_Abort_IT ,hi2cc, DevAddress,pData ,Size:$HAL_I2C_Master_Transmit_DMA ,hi2cc, DevAddress,pData ,Size:#HAL_I2C_Master_Receive_DMA ,hi2cc,pData ,Size:#HAL_I2C_Slave_Transmit_DMA ,hi2cc,pData ,Size:"HAL_I2C_Slave_Receive_DMA ,hi2cc, DevAddress, MemAddress, MemAddSize,pData ,Size:HAL_I2C_Mem_Write_DMA ,hi2cc, DevAddress, MemAddress, MemAddSize,pData ,Size:HAL_I2C_Mem_Read_DMAD ,hi2cc, DevAddress,pData ,Size:,  XferOptionsH( HAL_I2C_Master_Seq_Transmit_DMA ,hi2cc, DevAddress,pData ,Size:,  XferOptionsH'HAL_I2C_Master_Seq_Receive_DMA ,hi2cc,pData ,Size:,  XferOptionsH'HAL_I2C_Slave_Seq_Transmit_DMA ,hi2cc,pData ,Size:,  XferOptionsH&HAL_I2C_Slave_Seq_Receive_DMA ,hi2ccHAL_I2C_EV_IRQHandler ,hi2ccHAL_I2C_ER_IRQHandler ,hi2cc%HAL_I2C_MasterTxCpltCallback ,hi2cc%HAL_I2C_MasterRxCpltCallback ,hi2cc$HAL_I2C_SlaveTxCpltCallback ,hi2cc$HAL_I2C_SlaveRxCpltCallback ,hi2cc,TransferDirection,AddrMatchCodeHAL_I2C_AddrCallback ,hi2cc#HAL_I2C_ListenCpltCallbackT ,hi2cc"HAL_I2C_MemTxCpltCallback ,hi2cc"HAL_I2C_MemRxCpltCallback ,hi2ccHAL_I2C_ErrorCallbackV ,hi2cc"HAL_I2C_AbortCpltCallback ,hi2ccHAL_I2C_GetStateV ,hi2ccHAL_I2C_GetMode ,hi2ccHAL_I2C_GetErrorMPI2C_FLAG_MASK#PI2C_MIN_PCLK_FREQ_STANDARDPI2C_MIN_PCLK_FREQ_FASTPI2C_MIN_PCLK_FREQPI2C_CCR_CALCULATION"PI2C_FREQRANGEPI2C_RISE_TIMEPI2C_SPEED_STANDARDiPI2C_SPEED_FASTP I2C_SPEED+PI2C_7BIT_ADD_WRITEbPI2C_7BIT_ADD_READPI2C_10BIT_ADDRESSPI2C_10BIT_HEADER_WRITEPPI2C_10BIT_HEADER_READPI2C_MEM_ADD_MSBHPI2C_MEM_ADD_LSBIPIS_I2C_DUTY_CYCLE|PIS_I2C_ADDRESSING_MODEPIS_I2C_DUAL_ADDRESSPIS_I2C_GENERAL_CALLPIS_I2C_NO_STRETCHxPIS_I2C_MEMADD_SIZEMPIS_I2C_CLOCK_SPEEDSPIS_I2C_OWN_ADDRESS1PIS_I2C_OWN_ADDRESS2(P IS_I2C_TRANSFER_OPTIONS_REQUEST.P&IS_I2C_TRANSFER_OTHER_OPTIONS_REQUESTPI2C_CHECK_FLAGPI2C_CHECK_IT_SOURCEPSTM32F1xx_HAL_I2S_H8 Q "jModeG "j Standard "j DataFormat "j MCLKOutput "j AudioFreqB "jCPOLI2S_InitTypeDefqHAL_I2S_STATE_RESETHAL_I2S_STATE_READY!HAL_I2S_STATE_BUSYUHAL_I2S_STATE_BUSY_TXDHAL_I2S_STATE_BUSY_RXFHAL_I2S_STATE_TIMEOUTkHAL_I2S_STATE_ERROR HAL_I2S_StateTypeDef8 Q "j Instanceq "jInit "j pTxBuffPtr "j TxXferSize "j TxXferCountB "j pRxBuffPtr "j RxXferSize "j RxXferCountD "jhdmatx$ "jhdmarx& ""jLock ""jState "j ErrorCode-I2S_HandleTypeDefPHAL_I2S_ERROR_NONE-PHAL_I2S_ERROR_TIMEOUT0PHAL_I2S_ERROR_OVRhPHAL_I2S_ERROR_UDRtPHAL_I2S_ERROR_DMA PHAL_I2S_ERROR_PRESCALERPI2S_MODE_SLAVE_TXrPI2S_MODE_SLAVE_RXtPI2S_MODE_MASTER_TXPI2S_MODE_MASTER_RX!PI2S_STANDARD_PHILIPSPI2S_STANDARD_MSBPI2S_STANDARD_LSBPI2S_STANDARD_PCM_SHORTPI2S_STANDARD_PCM_LONGUPI2S_DATAFORMAT_16B$PI2S_DATAFORMAT_16B_EXTENDEDPI2S_DATAFORMAT_24BPI2S_DATAFORMAT_32BPI2S_MCLKOUTPUT_ENABLEVPI2S_MCLKOUTPUT_DISABLEPI2S_AUDIOFREQ_192KPI2S_AUDIOFREQ_96KPI2S_AUDIOFREQ_48KPI2S_AUDIOFREQ_44KPI2S_AUDIOFREQ_32KPI2S_AUDIOFREQ_22KPI2S_AUDIOFREQ_16KPI2S_AUDIOFREQ_11KPI2S_AUDIOFREQ_8KPI2S_AUDIOFREQ_DEFAULTpP I2S_CPOL_LOWPI2S_CPOL_HIGHP I2S_IT_TXEP I2S_IT_RXNEOP I2S_IT_ERRP I2S_FLAG_TXEPI2S_FLAG_RXNEP I2S_FLAG_UDR"P I2S_FLAG_OVRP I2S_FLAG_FRE0PI2S_FLAG_CHSIDEWP I2S_FLAG_BSYPI2S_FLAG_MASK%P__HAL_I2S_RESET_HANDLE_STATEP__HAL_I2S_ENABLEP__HAL_I2S_DISABLEP__HAL_I2S_ENABLE_ITP__HAL_I2S_DISABLE_IT P__HAL_I2S_GET_IT_SOURCErP__HAL_I2S_GET_FLAG/ P__HAL_I2S_CLEAR_OVRFLAG P__HAL_I2S_CLEAR_UDRFLAG ,hi2sS HAL_I2S_Init ,hi2sSHAL_I2S_DeInit. ,hi2sSHAL_I2S_MspInit ,hi2sSHAL_I2S_MspDeInit ,hi2sS,pData ,Size:, TimeoutHAL_I2S_Transmit ,hi2sS,pData ,Size:, TimeoutHAL_I2S_Receive ,hi2sS,pData ,Size:HAL_I2S_Transmit_IT ,hi2sS,pData ,Size:HAL_I2S_Receive_IT ,hi2sSHAL_I2S_IRQHandler ,hi2sS,pData ,Size:HAL_I2S_Transmit_DMA ,hi2sS,pData ,Size:HAL_I2S_Receive_DMAm ,hi2sSHAL_I2S_DMAPause ,hi2sSHAL_I2S_DMAResume" ,hi2sSHAL_I2S_DMAStop ,hi2sS#HAL_I2S_TxHalfCpltCallbackl ,hi2sSHAL_I2S_TxCpltCallback ,hi2sS#HAL_I2S_RxHalfCpltCallbackn ,hi2sSHAL_I2S_RxCpltCallback ,hi2sSHAL_I2S_ErrorCallbackF ,hi2sSHAL_I2S_GetStateF ,hi2sSHAL_I2S_GetError=PI2S_CHECK_FLAGPI2S_CHECK_IT_SOURCEP IS_I2S_MODEhPIS_I2S_STANDARD4PIS_I2S_DATA_FORMAT=PIS_I2S_MCLK_OUTPUTPIS_I2S_AUDIO_FREQP IS_I2S_CPOL_PSTM32F1xx_HAL_IWDG_H~8 Q "k Prescaler  "kReload[IWDG_InitTypeDef8 Q "k Instanceg "kInitIWDG_HandleTypeDefVPIWDG_PRESCALER_4PIWDG_PRESCALER_8PIWDG_PRESCALER_16PIWDG_PRESCALER_32PIWDG_PRESCALER_64PIWDG_PRESCALER_128PIWDG_PRESCALER_256P__HAL_IWDG_START"P__HAL_IWDG_RELOAD_COUNTER,hiwdgHAL_IWDG_Init|,hiwdgHAL_IWDG_Refresh;PIWDG_KEY_RELOAD$PIWDG_KEY_ENABLE4%PIWDG_KEY_WRITE_ACCESS_ENABLE&PIWDG_KEY_WRITE_ACCESS_DISABLE!PIWDG_ENABLE_WRITE_ACCESSo"PIWDG_DISABLE_WRITE_ACCESS PIS_IWDG_PRESCALERPIS_IWDG_RELOADsP__STM32F1xx_HAL_PWR_H8 Q "k PVDLevel "kModePWR_PVDTypeDefPPWR_EXTI_LINE_PVDGPPWR_PVDLEVEL_0fPPWR_PVDLEVEL_1ePPWR_PVDLEVEL_2dPPWR_PVDLEVEL_3cPPWR_PVDLEVEL_4bPPWR_PVDLEVEL_5aPPWR_PVDLEVEL_6`PPWR_PVDLEVEL_7_PPWR_PVD_MODE_NORMALPPWR_PVD_MODE_IT_RISING PPWR_PVD_MODE_IT_FALLING'PPWR_PVD_MODE_IT_RISING_FALLINGF"PPWR_PVD_MODE_EVENT_RISING#PPWR_PVD_MODE_EVENT_FALLING*P"PWR_PVD_MODE_EVENT_RISING_FALLING[PPWR_WAKEUP_PIN1PPWR_MAINREGULATOR_ONu!PPWR_LOWPOWERREGULATOR_ONPPWR_SLEEPENTRY_WFIPPWR_SLEEPENTRY_WFEPPWR_STOPENTRY_WFI4PPWR_STOPENTRY_WFE8P PWR_FLAG_WU8P PWR_FLAG_SBOPPWR_FLAG_PVDOP__HAL_PWR_GET_FLAGP__HAL_PWR_CLEAR_FLAGy%P__HAL_PWR_PVD_EXTI_ENABLE_IT&P__HAL_PWR_PVD_EXTI_DISABLE_ITu(P __HAL_PWR_PVD_EXTI_ENABLE_EVENT)P!__HAL_PWR_PVD_EXTI_DISABLE_EVENT/P'__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE0P(__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE.P&__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE/P'__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE6P.__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE7P/__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGET$P__HAL_PWR_PVD_EXTI_GET_FLAG&P__HAL_PWR_PVD_EXTI_CLEAR_FLAG)P!__HAL_PWR_PVD_EXTI_GENERATE_SWITnPIS_PWR_PVD_LEVELPIS_PWR_PVD_MODEPIS_PWR_WAKEUP_PINCPIS_PWR_REGULATORPIS_PWR_SLEEP_ENTRYPIS_PWR_STOP_ENTRYHAL_PWR_DeInit!HAL_PWR_EnableBkUpAccess!"HAL_PWR_DisableBkUpAccess, sConfigPVD HAL_PWR_ConfigPVDHAL_PWR_EnablePVD HAL_PWR_DisablePVD,  WakeUpPinx HAL_PWR_EnableWakeUpPins,  WakeUpPinx!HAL_PWR_DisableWakeUpPin,  Regulator, STOPEntry|HAL_PWR_EnterSTOPModei,  Regulator, SLEEPEntryGHAL_PWR_EnterSLEEPMode4!HAL_PWR_EnterSTANDBYMode"HAL_PWR_EnableSleepOnExit#HAL_PWR_DisableSleepOnExit$ HAL_PWR_EnableSEVOnPend!HAL_PWR_DisableSEVOnPendFHAL_PWR_PVD_IRQHandler=HAL_PWR_PVDCallback?P__STM32F1xx_HAL_RTC_HPIS_RTC_ASYNCH_PREDIVqPIS_RTC_HOUR24PIS_RTC_MINUTESGPIS_RTC_SECONDS]PIS_RTC_FORMATP IS_RTC_YEARAP IS_RTC_MONTHP IS_RTC_DATETP IS_RTC_ALARMPIS_RTC_CALIB_OUTPUTPRTC_TIMEOUT_VALUE^"PRTC_EXTI_LINE_ALARM_EVENT8 Q "lHours "lMinutes "lSecondsRTC_TimeTypeDef[8 Q "l AlarmTime# "lAlarmRTC_AlarmTypeDefHAL_RTC_STATE_RESETHAL_RTC_STATE_READYHAL_RTC_STATE_BUSY:HAL_RTC_STATE_TIMEOUTPHAL_RTC_STATE_ERRORHAL_RTCStateTypeDef 8 Q "l AsynchPrediv "lOutPut;RTC_InitTypeDefV8 Q "lWeekDay "lMonth "lDate5 "lYear"RTC_DateTypeDefl8 Q "l Instance[ "lInit "l DateToUpdate ""lLock ""lStateRTC_HandleTypeDefPRTC_AUTO_1_SECOND}PRTC_FORMAT_BINfPRTC_FORMAT_BCDvPRTC_MONTH_JANUARYbPRTC_MONTH_FEBRUARYPRTC_MONTH_MARCHPRTC_MONTH_APRILPRTC_MONTH_MAYPRTC_MONTH_JUNEPPRTC_MONTH_JULY>PRTC_MONTH_AUGUSTPRTC_MONTH_SEPTEMBERPRTC_MONTH_OCTOBERnPRTC_MONTH_NOVEMBERPRTC_MONTH_DECEMBERCPRTC_WEEKDAY_MONDAY.PRTC_WEEKDAY_TUESDAYPRTC_WEEKDAY_WEDNESDAYLPRTC_WEEKDAY_THURSDAY~PRTC_WEEKDAY_FRIDAY7PRTC_WEEKDAY_SATURDAYPRTC_WEEKDAY_SUNDAY"P RTC_ALARM_A`PRTC_OUTPUTSOURCE_NONE$PRTC_OUTPUTSOURCE_CALIBCLOCKePRTC_OUTPUTSOURCE_ALARM PRTC_OUTPUTSOURCE_SECONDxP RTC_IT_OWP RTC_IT_ALRAQP RTC_IT_SECP RTC_IT_TAMP1 PRTC_FLAG_RTOFFmP RTC_FLAG_RSFP RTC_FLAG_OWNPRTC_FLAG_ALRAFP RTC_FLAG_SECPRTC_FLAG_TAMP1FC%P__HAL_RTC_RESET_HANDLE_STATE*P"__HAL_RTC_WRITEPROTECTION_DISABLEj)P!__HAL_RTC_WRITEPROTECTION_ENABLE"P__HAL_RTC_ALARM_ENABLE_IT#P__HAL_RTC_ALARM_DISABLE_IT&P__HAL_RTC_ALARM_GET_IT_SOURCE!P__HAL_RTC_ALARM_GET_FLAG<P__HAL_RTC_ALARM_GET_IT#P__HAL_RTC_ALARM_CLEAR_FLAG'P__HAL_RTC_ALARM_EXTI_ENABLE_ITM(P __HAL_RTC_ALARM_EXTI_DISABLE_IT*P"__HAL_RTC_ALARM_EXTI_ENABLE_EVENTb+P#__HAL_RTC_ALARM_EXTI_DISABLE_EVENT1P)__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGEe2P*__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE0P(__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE1P)__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGEI8P0__HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE,9P1__HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE&P__HAL_RTC_ALARM_EXTI_GET_FLAG(P __HAL_RTC_ALARM_EXTI_CLEAR_FLAG+P#__HAL_RTC_ALARM_EXTI_GENERATE_SWIT!P__STM32F1xx_HAL_RTC_EX_H,P$HAL_RTCEx_TamperTimeStampIRQHandlerPIS_RTC_TAMPERPIS_RTC_TAMPER_TRIGGER"P IS_RTC_BKP"PIS_RTC_SMOOTH_CALIB_MINUS8 Q "lTamper "lTriggerRTC_TamperTypeDef}P RTC_TAMPER_1#PRTC_TAMPERTRIGGER_LOWLEVEL$PRTC_TAMPERTRIGGER_HIGHLEVELyP RTC_BKP_DR1jP RTC_BKP_DR2iP RTC_BKP_DR3hP RTC_BKP_DR4gP RTC_BKP_DR5fP RTC_BKP_DR6eP RTC_BKP_DR7dP RTC_BKP_DR8cP RTC_BKP_DR9bP RTC_BKP_DR108P RTC_BKP_DR117P RTC_BKP_DR126P RTC_BKP_DR135P RTC_BKP_DR144P RTC_BKP_DR153P RTC_BKP_DR162P RTC_BKP_DR171P RTC_BKP_DR180P RTC_BKP_DR19/P RTC_BKP_DR207P RTC_BKP_DR216P RTC_BKP_DR225P RTC_BKP_DR234P RTC_BKP_DR243P RTC_BKP_DR252P RTC_BKP_DR261P RTC_BKP_DR270P RTC_BKP_DR28/P RTC_BKP_DR29.P RTC_BKP_DR306P RTC_BKP_DR315P RTC_BKP_DR324P RTC_BKP_DR333P RTC_BKP_DR342P RTC_BKP_DR351P RTC_BKP_DR360P RTC_BKP_DR37/P RTC_BKP_DR38.P RTC_BKP_DR39-P RTC_BKP_DR405P RTC_BKP_DR414P RTC_BKP_DR423#P__HAL_RTC_TAMPER_ENABLE_IT$P__HAL_RTC_TAMPER_DISABLE_ITC'P__HAL_RTC_TAMPER_GET_IT_SOURCE!"P__HAL_RTC_TAMPER_GET_FLAG P__HAL_RTC_TAMPER_GET_IT_$P__HAL_RTC_TAMPER_CLEAR_FLAGS#P__HAL_RTC_SECOND_ENABLE_IT$P__HAL_RTC_SECOND_DISABLE_ITP'P__HAL_RTC_SECOND_GET_IT_SOURCE."P__HAL_RTC_SECOND_GET_FLAG$P__HAL_RTC_SECOND_CLEAR_FLAG`%P__HAL_RTC_OVERFLOW_ENABLE_IT&P__HAL_RTC_OVERFLOW_DISABLE_IT)P!__HAL_RTC_OVERFLOW_GET_IT_SOURCEr$P__HAL_RTC_OVERFLOW_GET_FLAG/&P__HAL_RTC_OVERFLOW_CLEAR_FLAG ,hrtc,sTamperHAL_RTCEx_SetTamper ,hrtc,sTamperHAL_RTCEx_SetTamper_IT ,hrtc, Tamperj#HAL_RTCEx_DeactivateTamper ,hrtc#HAL_RTCEx_TamperIRQHandlerh ,hrtc'HAL_RTCEx_Tamper1EventCallback ,hrtc, Timeout&HAL_RTCEx_PollForTamper1Event ,hrtcHAL_RTCEx_SetSecond_IT ,hrtc#HAL_RTCEx_DeactivateSecond% ,hrtc HAL_RTCEx_RTCIRQHandler ,hrtc#HAL_RTCEx_RTCEventCallback ,hrtc( HAL_RTCEx_RTCEventErrorCallbacko ,hrtc, BackupRegister( , Data]HAL_RTCEx_BKUPWriteL ,hrtc, BackupRegister(HAL_RTCEx_BKUPRead ,hrtc, SmoothCalibPeriod, SmoothCalibPlusPulses@$, SmouthCalibMinusPulsesValue!HAL_RTCEx_SetSmoothCalib ,hrtc HAL_RTC_Init ,hrtcHAL_RTC_DeInit ,hrtcHAL_RTC_MspInit ,hrtcHAL_RTC_MspDeInit ,hrtc,sTime, FormatjHAL_RTC_SetTime ,hrtc,sTime, FormatjHAL_RTC_GetTime ,hrtc,sDate, FormatjHAL_RTC_SetDate ,hrtc,sDate, FormatjHAL_RTC_GetDate ,hrtc,sAlarme, FormatjHAL_RTC_SetAlarm3 ,hrtc,sAlarme, FormatjHAL_RTC_SetAlarm_IT1 ,hrtc, Alarm HAL_RTC_DeactivateAlarmW ,hrtc,sAlarme, Alarm, FormatjHAL_RTC_GetAlarm? ,hrtc HAL_RTC_AlarmIRQHandler ,hrtc, Timeout#HAL_RTC_PollForAlarmAEventJ ,hrtc$HAL_RTC_AlarmAEventCallback ,hrtcHAL_RTC_GetState+ ,hrtcHAL_RTC_WaitForSynchroPSTM32F1xx_HAL_PCCARD_HHAL_PCCARD_STATE_RESET.HAL_PCCARD_STATE_READY<HAL_PCCARD_STATE_BUSYpHAL_PCCARD_STATE_ERROR' HAL_PCCARD_StateTypeDef"HAL_PCCARD_STATUS_SUCCESS/"HAL_PCCARD_STATUS_ONGOING7 HAL_PCCARD_STATUS_ERROR"HAL_PCCARD_STATUS_TIMEOUT!!HAL_PCCARD_StatusTypeDef\8 Q "n Instancel " nInit  ""nState ""nLockPCCARD_HandleTypeDef(P __HAL_PCCARD_RESET_HANDLE_STATE!,hpccard,ComSpaceTimingB,AttSpaceTiming8,IOSpaceTimingHAL_PCCARD_Init,hpccardHAL_PCCARD_DeInitI,hpccardHAL_PCCARD_MspInit,hpccardHAL_PCCARD_MspDeInit,hpccard,CompactFlash_ID,pStatusHAL_PCCARD_Read_ID,hpccard,pBuffer,SectorAddress,pStatus HAL_PCCARD_Write_Sector,hpccard,pBuffer,SectorAddress,pStatusHAL_PCCARD_Read_Sector1,hpccard,SectorAddress,pStatus HAL_PCCARD_Erase_Sector,hpccardHAL_PCCARD_Reset,hpccardHAL_PCCARD_IRQHandler,hpccardHAL_PCCARD_ITCallback,hpccardHAL_PCCARD_GetStatea,hpccardHAL_PCCARD_GetStatus,hpccardHAL_PCCARD_ReadStatus~PPCCARD_DEVICE_ADDRESS'PPCCARD_ATTRIBUTE_SPACE_ADDRESS$PPCCARD_COMMON_SPACE_ADDRESS PPCCARD_IO_SPACE_ADDRESS%PPCCARD_IO_SPACE_PRIMARY_ADDR'P ATA_DATAlPATA_SECTOR_COUNTPATA_SECTOR_NUMBER|PATA_CYLINDER_LOWPATA_CYLINDER_HIGHPATA_CARD_HEADPATA_STATUS_CMDc!PATA_STATUS_CMD_ALTERNATEPPATA_COMMON_DATA_AREAPATA_CARD_CONFIGURATIONPATA_READ_SECTOR_CMDPATA_WRITE_SECTOR_CMDPATA_ERASE_SECTOR_CMDPATA_IDENTIFY_CMDPPCCARD_TIMEOUT_ERRORP PCCARD_BUSYfP PCCARD_PROGRP PCCARD_READY2PPCCARD_SECTOR_SIZE1P HAL_CF_InitPHAL_CF_DeInitXPHAL_CF_MspInitPHAL_CF_MspDeInit"PHAL_CF_Read_ID+PHAL_CF_Write_SectorPHAL_CF_Read_Sector@PHAL_CF_Erase_SectorP HAL_CF_ResetPHAL_CF_IRQHandlerPHAL_CF_ITCallbackPHAL_CF_GetStatepPHAL_CF_GetStatusPHAL_CF_ReadStatusPHAL_CF_STATUS_SUCCESS)PHAL_CF_STATUS_ONGOING1PHAL_CF_STATUS_ERRORPHAL_CF_STATUS_TIMEOUTPHAL_CF_StatusTypeDefRPCF_DEVICE_ADDRESS#PCF_ATTRIBUTE_SPACE_ADDRESS PCF_COMMON_SPACE_ADDRESSPCF_IO_SPACE_ADDRESS!PCF_IO_SPACE_PRIMARY_ADDRSPCF_TIMEOUT_ERRORPCF_BUSYP CF_PROGRIP CF_READY^PCF_SECTOR_SIZE]PSTM32F1xx_HAL_SD_HPSTM32F1xx_LL_SDMMC_Hr8 Q "o ClockEdged "o ClockBypassc "oClockPowerSave3 "oBusWide "oHardwareFlowControl  "o ClockDivSDIO_InitTypeDef8 Q "o Argument| "o CmdIndex "o Responsep "oWaitForInterrupt& "oCPSMSDIO_CmdInitTypeDef8 Q "o DataTimeOutq "o DataLength "oDataBlockSize "o TransferDirN "o TransferMode "oDPSMSDIO_DataInitTypeDefPSDMMC_ERROR_NONE!PSDMMC_ERROR_CMD_CRC_FAILY"PSDMMC_ERROR_DATA_CRC_FAIL$PSDMMC_ERROR_CMD_RSP_TIMEOUT+!PSDMMC_ERROR_DATA_TIMEOUT? PSDMMC_ERROR_TX_UNDERRUNcPSDMMC_ERROR_RX_OVERRUN$PSDMMC_ERROR_ADDR_MISALIGNED"PSDMMC_ERROR_BLOCK_LEN_ERR"PSDMMC_ERROR_ERASE_SEQ_ERR$PSDMMC_ERROR_BAD_ERASE_PARAMs)P!SDMMC_ERROR_WRITE_PROT_VIOLATION'PSDMMC_ERROR_LOCK_UNLOCK_FAILED{#PSDMMC_ERROR_COM_CRC_FAILED PSDMMC_ERROR_ILLEGAL_CMD$PSDMMC_ERROR_CARD_ECC_FAILEDPSDMMC_ERROR_CC_ERR(P SDMMC_ERROR_GENERAL_UNKNOWN_ERR)P!SDMMC_ERROR_STREAM_READ_UNDERRUN)P!SDMMC_ERROR_STREAM_WRITE_OVERRUN&PSDMMC_ERROR_CID_CSD_OVERWRITE"PSDMMC_ERROR_WP_ERASE_SKIP&PSDMMC_ERROR_CARD_ECC_DISABLED PSDMMC_ERROR_ERASE_RESET PSDMMC_ERROR_AKE_SEQ_ERR&PSDMMC_ERROR_INVALID_VOLTRANGE&PSDMMC_ERROR_ADDR_OUT_OF_RANGE+P#SDMMC_ERROR_REQUEST_NOT_APPLICABLE&&PSDMMC_ERROR_INVALID_PARAMETER(P SDMMC_ERROR_UNSUPPORTED_FEATUREPSDMMC_ERROR_BUSYPSDMMC_ERROR_DMAPSDMMC_ERROR_TIMEOUT PSDMMC_CMD_GO_IDLE_STATEPSDMMC_CMD_SEND_OP_CONDPSDMMC_CMD_ALL_SEND_CIDPSDMMC_CMD_SET_REL_ADDRPSDMMC_CMD_SET_DSRo$PSDMMC_CMD_SDMMC_SEN_OP_CONDUPSDMMC_CMD_HS_SWITCH!PSDMMC_CMD_SEL_DESEL_CARDl"PSDMMC_CMD_HS_SEND_EXT_CSDPSDMMC_CMD_SEND_CSD>PSDMMC_CMD_SEND_CIDH&PSDMMC_CMD_READ_DAT_UNTIL_STOP$PSDMMC_CMD_STOP_TRANSMISSION@PSDMMC_CMD_SEND_STATUS."PSDMMC_CMD_HS_BUSTEST_READ$PSDMMC_CMD_GO_INACTIVE_STATEgPSDMMC_CMD_SET_BLOCKLEN$PSDMMC_CMD_READ_SINGLE_BLOCK"PSDMMC_CMD_READ_MULT_BLOCK #PSDMMC_CMD_HS_BUSTEST_WRITE'PSDMMC_CMD_WRITE_DAT_UNTIL_STOP6"PSDMMC_CMD_SET_BLOCK_COUNT%PSDMMC_CMD_WRITE_SINGLE_BLOCK#PSDMMC_CMD_WRITE_MULT_BLOCKPSDMMC_CMD_PROG_CID:PSDMMC_CMD_PROG_CSD0!PSDMMC_CMD_SET_WRITE_PROT!PSDMMC_CMD_CLR_WRITE_PROT&"PSDMMC_CMD_SEND_WRITE_PROT%PSDMMC_CMD_SD_ERASE_GRP_START#PSDMMC_CMD_SD_ERASE_GRP_END"PSDMMC_CMD_ERASE_GRP_START PSDMMC_CMD_ERASE_GRP_ENDPSDMMC_CMD_ERASE7PSDMMC_CMD_FAST_IO~PSDMMC_CMD_GO_IRQ_STATEPSDMMC_CMD_LOCK_UNLOCKGPSDMMC_CMD_APP_CMDPSDMMC_CMD_GEN_CMDPSDMMC_CMD_NO_CMD&PSDMMC_CMD_APP_SD_SET_BUSWIDTH PSDMMC_CMD_SD_APP_STATUS}/P'SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS!PSDMMC_CMD_SD_APP_OP_COND=-P%SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT"PSDMMC_CMD_SD_APP_SEND_SCR"PSDMMC_CMD_SDMMC_RW_DIRECT$PSDMMC_CMD_SDMMC_RW_EXTENDEDc!PSDMMC_CMD_SD_APP_GET_MKBF!PSDMMC_CMD_SD_APP_GET_MIDF%PSDMMC_CMD_SD_APP_SET_CER_RN1%PSDMMC_CMD_SD_APP_GET_CER_RN2 &PSDMMC_CMD_SD_APP_SET_CER_RES2&PSDMMC_CMD_SD_APP_GET_CER_RES14P,SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCKb5P-SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK&PSDMMC_CMD_SD_APP_SECURE_ERASE,P$SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA*P"SDMMC_CMD_SD_APP_SECURE_WRITE_MKBc$PSDMMC_OCR_ADDR_OUT_OF_RANGEM"PSDMMC_OCR_ADDR_MISALIGNED, PSDMMC_OCR_BLOCK_LEN_ERR PSDMMC_OCR_ERASE_SEQ_ERR"PSDMMC_OCR_BAD_ERASE_PARAM'PSDMMC_OCR_WRITE_PROT_VIOLATION6%PSDMMC_OCR_LOCK_UNLOCK_FAILED%!PSDMMC_OCR_COM_CRC_FAILEDkPSDMMC_OCR_ILLEGAL_CMD^"PSDMMC_OCR_CARD_ECC_FAILED;PSDMMC_OCR_CC_ERROR"(P SDMMC_OCR_GENERAL_UNKNOWN_ERROR'PSDMMC_OCR_STREAM_READ_UNDERRUN`'PSDMMC_OCR_STREAM_WRITE_OVERRUN3$PSDMMC_OCR_CID_CSD_OVERWRITEP PSDMMC_OCR_WP_ERASE_SKIP{$PSDMMC_OCR_CARD_ECC_DISABLEDPSDMMC_OCR_ERASE_RESET9 PSDMMC_OCR_AKE_SEQ_ERRORPSDMMC_OCR_ERRORBITS'PSDMMC_R6_GENERAL_UNKNOWN_ERROR_PSDMMC_R6_ILLEGAL_CMD PSDMMC_R6_COM_CRC_FAILED PSDMMC_VOLTAGE_WINDOW_SDPSDMMC_HIGH_CAPACITYPSDMMC_STD_CAPACITY<PSDMMC_CHECK_PATTERN PSD_SWITCH_1_8V_CAPACITYPSDMMC_MAX_VOLT_TRIALkPSDMMC_MAX_TRIALPSDMMC_ALLZEROPSDMMC_WIDE_BUS_SUPPORT!PSDMMC_SINGLE_BUS_SUPPORT!PSDMMC_CARD_LOCKEDPSDMMC_DATATIMEOUTPSDMMC_0TO7BITSPSDMMC_8TO15BITSgPSDMMC_16TO23BITS7PSDMMC_24TO31BITS9PSDMMC_MAX_DATA_LENGTHNPSDMMC_HALFFIFOPSDMMC_HALFFIFOBYTES PSDIO_CCCC_ERASEDPSDIO_CMDTIMEOUT$PSDIO_MAXERASETIMEOUT!PSDIO_STOPTRANSFERTIMEOUT;PSDIO_CLOCK_EDGE_RISING PSDIO_CLOCK_EDGE_FALLINGPIS_SDIO_CLOCK_EDGE>"PSDIO_CLOCK_BYPASS_DISABLE!PSDIO_CLOCK_BYPASS_ENABLEjPIS_SDIO_CLOCK_BYPASS}&PSDIO_CLOCK_POWER_SAVE_DISABLE%PSDIO_CLOCK_POWER_SAVE_ENABLE!PIS_SDIO_CLOCK_POWER_SAVE,PSDIO_BUS_WIDE_1BPSDIO_BUS_WIDE_4BPSDIO_BUS_WIDE_8BPIS_SDIO_BUS_WIDE+P#SDIO_HARDWARE_FLOW_CONTROL_DISABLEA*P"SDIO_HARDWARE_FLOW_CONTROL_ENABLE&PIS_SDIO_HARDWARE_FLOW_CONTROLPIS_SDIO_CLKDIViPIS_SDIO_CMD_INDEXuPSDIO_RESPONSE_NOPSDIO_RESPONSE_SHORTPSDIO_RESPONSE_LONGPIS_SDIO_RESPONSEP SDIO_WAIT_NOP SDIO_WAIT_ITPSDIO_WAIT_PENDfP IS_SDIO_WAITPSDIO_CPSM_DISABLEPSDIO_CPSM_ENABLEP IS_SDIO_CPSMP SDIO_RESP1P SDIO_RESP2P SDIO_RESP3P SDIO_RESP4P IS_SDIO_RESPPIS_SDIO_DATA_LENGTHPSDIO_DATABLOCK_SIZE_1B PSDIO_DATABLOCK_SIZE_2BPSDIO_DATABLOCK_SIZE_4BPSDIO_DATABLOCK_SIZE_8B PSDIO_DATABLOCK_SIZE_16B PSDIO_DATABLOCK_SIZE_32B PSDIO_DATABLOCK_SIZE_64B!PSDIO_DATABLOCK_SIZE_128B!PSDIO_DATABLOCK_SIZE_256B!PSDIO_DATABLOCK_SIZE_512B"PSDIO_DATABLOCK_SIZE_1024B"PSDIO_DATABLOCK_SIZE_2048B}"PSDIO_DATABLOCK_SIZE_4096Bx"PSDIO_DATABLOCK_SIZE_8192Bw#PSDIO_DATABLOCK_SIZE_16384BCPIS_SDIO_BLOCK_SIZE"PSDIO_TRANSFER_DIR_TO_CARD"PSDIO_TRANSFER_DIR_TO_SDIOPIS_SDIO_TRANSFER_DIRw!PSDIO_TRANSFER_MODE_BLOCKZ"PSDIO_TRANSFER_MODE_STREAMPIS_SDIO_TRANSFER_MODE/PSDIO_DPSM_DISABLEPSDIO_DPSM_ENABLEP IS_SDIO_DPSM"PSDIO_READ_WAIT_MODE_DATA2, PSDIO_READ_WAIT_MODE_CLKPIS_SDIO_READWAIT_MODECPSDIO_IT_CCRCFAILPSDIO_IT_DCRCFAILPSDIO_IT_CTIMEOUTPSDIO_IT_DTIMEOUTPSDIO_IT_TXUNDERRPSDIO_IT_RXOVERRPSDIO_IT_CMDREND&PSDIO_IT_CMDSENTPSDIO_IT_DATAEND2PSDIO_IT_STBITERRPSDIO_IT_DBCKEND8PSDIO_IT_CMDACTyPSDIO_IT_TXACTPSDIO_IT_RXACTPSDIO_IT_TXFIFOHEPSDIO_IT_RXFIFOHFPSDIO_IT_TXFIFOF PSDIO_IT_RXFIFOFPSDIO_IT_TXFIFOEPSDIO_IT_RXFIFOEPSDIO_IT_TXDAVLRPSDIO_IT_RXDAVLTPSDIO_IT_SDIOITYPSDIO_IT_CEATAENDPSDIO_FLAG_CCRCFAILiPSDIO_FLAG_DCRCFAILhPSDIO_FLAG_CTIMEOUT6PSDIO_FLAG_DTIMEOUT5PSDIO_FLAG_TXUNDERR$PSDIO_FLAG_RXOVERRjPSDIO_FLAG_CMDRENDPSDIO_FLAG_CMDSENTPSDIO_FLAG_DATAENDPSDIO_FLAG_STBITERR1PSDIO_FLAG_DBCKENDPSDIO_FLAG_CMDACTPSDIO_FLAG_TXACT"PSDIO_FLAG_RXACT$PSDIO_FLAG_TXFIFOHECPSDIO_FLAG_RXFIFOHFDPSDIO_FLAG_TXFIFOFPSDIO_FLAG_RXFIFOFPSDIO_FLAG_TXFIFOEPSDIO_FLAG_RXFIFOEPSDIO_FLAG_TXDAVLPSDIO_FLAG_RXDAVLPSDIO_FLAG_SDIOITPSDIO_FLAG_CEATAENDkPSDIO_STATIC_FLAGSPSDIO_STATIC_CMD_FLAGSLPSDIO_STATIC_DATA_FLAGSP SDIO_OFFSET`P CLKCR_OFFSETPCLKEN_BITNUMBER9PCLKCR_CLKEN_BBP CMD_OFFSETPSDIOSUSPEND_BITNUMBERIPCMD_SDIOSUSPEND_BB@PENCMDCOMPL_BITNUMBERPCMD_ENCMDCOMPL_BBPNIEN_BITNUMBER~P CMD_NIEN_BBuPATACMD_BITNUMBERPCMD_ATACMD_BBP DCTRL_OFFSETPDMAEN_BITNUMBERAPDCTRL_DMAEN_BBPRWSTART_BITNUMBERkPDCTRL_RWSTART_BBPRWSTOP_BITNUMBERPDCTRL_RWSTOP_BBPRWMOD_BITNUMBERPDCTRL_RWMOD_BBkPSDIOEN_BITNUMBERPDCTRL_SDIOEN_BB0PCLKCR_CLEAR_MASKPDCTRL_CLEAR_MASKPCMD_CLEAR_MASKPSDIO_INIT_CLK_DIVlPSDIO_TRANSFER_CLK_DIV3P__SDIO_ENABLEP__SDIO_DISABLEoP__SDIO_DMA_ENABLEP__SDIO_DMA_DISABLE6P__SDIO_ENABLE_ITP__SDIO_DISABLE_ITmP__SDIO_GET_FLAGP__SDIO_CLEAR_FLAG}P__SDIO_GET_ITP__SDIO_CLEAR_IT%P__SDIO_START_READWAIT_ENABLE&P__SDIO_START_READWAIT_DISABLE$P__SDIO_STOP_READWAIT_ENABLEM%P__SDIO_STOP_READWAIT_DISABLE P__SDIO_OPERATION_ENABLE!P__SDIO_OPERATION_DISABLEK"P__SDIO_SUSPEND_CMD_ENABLE#P__SDIO_SUSPEND_CMD_DISABLE+P#__SDIO_CEATA_CMD_COMPLETION_ENABLEK,P$__SDIO_CEATA_CMD_COMPLETION_DISABLEP__SDIO_CEATA_ENABLE_IT P__SDIO_CEATA_DISABLE_IT$P__SDIO_CEATA_SENDCMD_ENABLE%P__SDIO_CEATA_SENDCMD_DISABLE9,SDIOx ,Init SDIO_Init,SDIOx SDIO_ReadFIFO,SDIOx , pWriteDataSDIO_WriteFIFO,SDIOx SDIO_PowerState_ON,,SDIOx SDIO_PowerState_OFF,SDIOx SDIO_GetPowerState,SDIOx ,CommandSDIO_SendCommand,SDIOx SDIO_GetCommandResponse,SDIOx ,  ResponseSDIO_GetResponse,SDIOx ,DataOSDIO_ConfigDatal,SDIOx SDIO_GetDataCounter,SDIOx SDIO_GetFIFOCount,SDIOx , SDIO_ReadWaitMode"SDIO_SetSDMMCReadWaitMode,SDIOx ,  BlockSizeGSDMMC_CmdBlockLength,SDIOx , ReadAddL!SDMMC_CmdReadSingleBlock,SDIOx , ReadAddL SDMMC_CmdReadMultiBlocka,SDIOx ,  WriteAdd"SDMMC_CmdWriteSingleBlockw,SDIOx ,  WriteAdd!SDMMC_CmdWriteMultiBlock,SDIOx ,  StartAddSDMMC_CmdEraseStartAdd,SDIOx ,  StartAdd!SDMMC_CmdSDEraseStartAdd3,SDIOx , EndAddSDMMC_CmdEraseEndAdd,SDIOx , EndAddSDMMC_CmdSDEraseEndAdd.,SDIOx SDMMC_CmdErase,SDIOx SDMMC_CmdStopTransfer,SDIOx ,(Addr:SDMMC_CmdSelDesel,SDIOx SDMMC_CmdGoIdleState,SDIOx SDMMC_CmdOperCond,SDIOx ,  ArgumentSDMMC_CmdAppCommand,SDIOx ,  Argument SDMMC_CmdAppOperCommand],SDIOx ,  BusWidthSDMMC_CmdBusWidth,SDIOx SDMMC_CmdSendSCRo,SDIOx SDMMC_CmdSendCID,SDIOx ,  ArgumentSDMMC_CmdSendCSD},SDIOx ,pRCASDMMC_CmdSetRelAdd,SDIOx ,  ArgumentSDMMC_CmdSendStatus,SDIOx SDMMC_CmdStatusRegister ,SDIOx ,  ArgumentSDMMC_CmdOpConditions,SDIOx ,  ArgumentSDMMC_CmdSwitchqHAL_SD_STATE_RESETLHAL_SD_STATE_READYZHAL_SD_STATE_TIMEOUTHAL_SD_STATE_BUSY!HAL_SD_STATE_PROGRAMMINGHAL_SD_STATE_RECEIVING+HAL_SD_STATE_TRANSFERdHAL_SD_STATE_ERROREHAL_SD_StateTypeDef HAL_SD_CardStateTypeDef}PHAL_SD_CARD_READY#PHAL_SD_CARD_IDENTIFICATIONPHAL_SD_CARD_STANDBYPHAL_SD_CARD_TRANSFERPHAL_SD_CARD_SENDINGPHAL_SD_CARD_RECEIVINGb PHAL_SD_CARD_PROGRAMMING!PHAL_SD_CARD_DISCONNECTEDPHAL_SD_CARD_ERROR|PSD_InitTypeDeftP SD_TypeDef8 Q "r CardTypeg "r CardVersion "rClass "r RelCardAdd "r BlockNbrv "r BlockSize "r LogBlockNbrN "r LogBlockSizeHAL_SD_CardInfoTypeDef8 Q "r Instance6 "rInit ""rLock "r pTxBuffPtrr "r TxXferSizey "r pRxBuffPtrt "r RxXferSize{ "rContext ""rStatei "r ErrorCode "rhdmatx "rhdmarx " rSdCard <"rCSDk <"rCIDuSD_HandleTypeDef8 Q "r CSDStruct "rSysSpecVersion "r Reserved1 "rTAAC^ "rNSACR "rMaxBusClkFrec{ "rCardComdClasses "r RdBlockLen "rPartBlockReadg "rWrBlockMisaligny "rRdBlockMisalign "rDSRImpl "r Reserved2 "r DeviceSizey "rMaxRdCurrentVDDMin "rMaxRdCurrentVDDMax "rMaxWrCurrentVDDMin "rMaxWrCurrentVDDMax "rDeviceSizeMulL "r EraseGrSize% "r EraseGrMul "rWrProtectGrSizec "rWrProtectGrEnable "r ManDeflECC  "r WrSpeedFact1 "rMaxWrBlockLenl "rWriteBlockPaPartial "r Reserved3 "rContentProtectAppli "rFileFormatGroupk "r CopyFlagZ "rPermWrProtect' "rTempWrProtect% "r FileFormat "rECC "rCSD_CRC` "r Reserved4HAL_SD_CardCSDTypeDef8 Q "sManufacturerIDA "s OEM_AppliID "s ProdName1w "s ProdName2} "sProdRev "sProdSN "s Reserved1T "s ManufactDate  "sCID_CRC "s Reserved2SHAL_SD_CardCIDTypeDef8 Q "s DataBusWidth "s SecuredModee "s CardType "sProtectedAreaSize "s SpeedClass "sPerformanceMove "sAllocationUnitSizef "s EraseSize% "s EraseTimeout "s EraseOffset^!HAL_SD_CardStatusTypeDefP BLOCKSIZEPHAL_SD_ERROR_NONEf"PHAL_SD_ERROR_CMD_CRC_FAIL#PHAL_SD_ERROR_DATA_CRC_FAIL%PHAL_SD_ERROR_CMD_RSP_TIMEOUT"PHAL_SD_ERROR_DATA_TIMEOUT!PHAL_SD_ERROR_TX_UNDERRUN PHAL_SD_ERROR_RX_OVERRUNP%PHAL_SD_ERROR_ADDR_MISALIGNED)#PHAL_SD_ERROR_BLOCK_LEN_ERR#PHAL_SD_ERROR_ERASE_SEQ_ERR%PHAL_SD_ERROR_BAD_ERASE_PARAM*P"HAL_SD_ERROR_WRITE_PROT_VIOLATION3(P HAL_SD_ERROR_LOCK_UNLOCK_FAILED"$PHAL_SD_ERROR_COM_CRC_FAILEDh!PHAL_SD_ERROR_ILLEGAL_CMD[%PHAL_SD_ERROR_CARD_ECC_FAILED8PHAL_SD_ERROR_CC_ERR)P!HAL_SD_ERROR_GENERAL_UNKNOWN_ERR*P"HAL_SD_ERROR_STREAM_READ_UNDERRUN]*P"HAL_SD_ERROR_STREAM_WRITE_OVERRUN0'PHAL_SD_ERROR_CID_CSD_OVERWRITEM#PHAL_SD_ERROR_WP_ERASE_SKIPx'PHAL_SD_ERROR_CARD_ECC_DISABLED!PHAL_SD_ERROR_ERASE_RESET6!PHAL_SD_ERROR_AKE_SEQ_ERR''PHAL_SD_ERROR_INVALID_VOLTRANGEd'PHAL_SD_ERROR_ADDR_OUT_OF_RANGEJ,P$HAL_SD_ERROR_REQUEST_NOT_APPLICABLEPHAL_SD_ERROR_PARAM#)P!HAL_SD_ERROR_UNSUPPORTED_FEATUREPHAL_SD_ERROR_BUSYSPHAL_SD_ERROR_DMAPHAL_SD_ERROR_TIMEOUTiPSD_CONTEXT_NONE%PSD_CONTEXT_READ_SINGLE_BLOCK'PSD_CONTEXT_READ_MULTIPLE_BLOCKd&PSD_CONTEXT_WRITE_SINGLE_BLOCK(P SD_CONTEXT_WRITE_MULTIPLE_BLOCKPSD_CONTEXT_ITPSD_CONTEXT_DMAcP CARD_SDSCPCARD_SDHC_SDXCP CARD_SECURED/P CARD_V1_XP CARD_V2_X$P__HAL_SD_RESET_HANDLE_STATE?P__HAL_SD_ENABLEP__HAL_SD_DISABLEP__HAL_SD_DMA_ENABLEP__HAL_SD_DMA_DISABLEP__HAL_SD_ENABLE_ITP__HAL_SD_DISABLE_ITP__HAL_SD_GET_FLAGhP__HAL_SD_CLEAR_FLAGP__HAL_SD_GET_ITP__HAL_SD_CLEAR_IT^ ,hsd HAL_SD_Init ,hsdHAL_SD_InitCard ,hsdHAL_SD_DeInitg ,hsdHAL_SD_MspInit ,hsdHAL_SD_MspDeInit1 ,hsd,pData,  BlockAdd, NumberOfBlocksG, TimeoutHAL_SD_ReadBlocks ,hsd,pData,  BlockAdd, NumberOfBlocksG, TimeoutHAL_SD_WriteBlocks1 ,hsd, BlockStartAdd,  BlockEndAdd HAL_SD_Erase ,hsd,pData,  BlockAdd, NumberOfBlocksGHAL_SD_ReadBlocks_IT ,hsd,pData,  BlockAdd, NumberOfBlocksGHAL_SD_WriteBlocks_IT/ ,hsd,pData,  BlockAdd, NumberOfBlocksGHAL_SD_ReadBlocks_DMA ,hsd,pData,  BlockAdd, NumberOfBlocksGHAL_SD_WriteBlocks_DMA ,hsdHAL_SD_IRQHandler ,hsdHAL_SD_TxCpltCallback( ,hsdHAL_SD_RxCpltCallback* ,hsdHAL_SD_ErrorCallback ,hsdHAL_SD_AbortCallback ,hsd,  WideMode&HAL_SD_ConfigWideBusOperation ,hsd,  SpeedModeW'HAL_SD_ConfigSpeedBusOperation` ,hsd, pSDstatusHAL_SD_SendSDStatus ,hsdHAL_SD_GetCardState ,hsd ,pCIDHAL_SD_GetCardCID2 ,hsd ,pCSDHAL_SD_GetCardCSD( ,hsd,pStatusHAL_SD_GetCardStatusx ,hsd, pCardInfoIHAL_SD_GetCardInfot ,hsdHAL_SD_GetState ,hsdHAL_SD_GetErrorv ,hsd HAL_SD_Abort ,hsdHAL_SD_Abort_ITPSTM32F1xx_HAL_NAND_HHAL_NAND_STATE_RESETHAL_NAND_STATE_READYHAL_NAND_STATE_BUSYHAL_NAND_STATE_ERRORHAL_NAND_StateTypeDefq8 Q "t Maker_Id "t Device_Id: "t Third_Id "t Fourth_IdNAND_IDTypeDef'8 Q "tPage "tPlane "tBlockNAND_AddressTypeDef8 Q "t PageSizen "tSpareAreaSizem "t BlockSize "t BlockNbry "t PlaneNbrt "t PlaneSize ""tExtraCommandEnableS!NAND_DeviceConfigTypeDef8 Q "t Instance: "tInit ""tLock ""tStatem "tConfigNAND_HandleTypeDef`&P__HAL_NAND_RESET_HANDLE_STATE,hnand,ComSpace_Timing,AttSpace_TimingHAL_NAND_Init,hnandHAL_NAND_DeInit,hnand,pDeviceConfigHAL_NAND_ConfigDeviced,hnand, pNAND_IDDHAL_NAND_Read_ID,hnandHAL_NAND_MspInitP,hnandHAL_NAND_MspDeInit,hnandHAL_NAND_IRQHandlerd,hnandHAL_NAND_ITCallbackd,hnandHAL_NAND_Reset,hnand, pAddress,pBuffer, NumPageToReadHAL_NAND_Read_Page_8b,hnand, pAddress,pBuffer, NumPageToWriteHHAL_NAND_Write_Page_8b(,hnand, pAddress,pBuffer, NumSpareAreaToRead#HAL_NAND_Read_SpareArea_8b,hnand, pAddress,pBuffer, NumSpareAreaTowrite'$HAL_NAND_Write_SpareArea_8b',hnand, pAddress,pBuffer, NumPageToReadHAL_NAND_Read_Page_16b,hnand, pAddress,pBuffer, NumPageToWriteH HAL_NAND_Write_Page_16b,hnand, pAddress,pBuffer, NumSpareAreaToRead$HAL_NAND_Read_SpareArea_16b,hnand, pAddress,pBuffer, NumSpareAreaTowrite'%HAL_NAND_Write_SpareArea_16b,hnand, pAddressHAL_NAND_Erase_Block,hnand, pAddressHAL_NAND_Address_Inc,hnandHAL_NAND_ECC_Enable,hnandHAL_NAND_ECC_Disable.,hnand,ECCval, TimeoutHAL_NAND_GetECC+,hnandHAL_NAND_GetState,hnandHAL_NAND_Read_StatusP NAND_DEVICE1RP NAND_DEVICE2QPNAND_WRITE_TIMEOUTP CMD_AREAoP ADDR_AREA&PNAND_CMD_AREA_AAPNAND_CMD_AREA_B@PNAND_CMD_AREA_C?PNAND_CMD_AREA_TRUE1 PNAND_CMD_WRITE0?PNAND_CMD_WRITE_TRUE1PNAND_CMD_ERASE0ZPNAND_CMD_ERASE1YPNAND_CMD_READIDQPNAND_CMD_STATUSPNAND_CMD_LOCK_STATUSPNAND_CMD_RESETyPNAND_VALID_ADDRESSRPNAND_INVALID_ADDRESSPNAND_TIMEOUT_ERRORP NAND_BUSYP NAND_ERRORP NAND_READYPARRAY_ADDRESSPCOLUMN_ADDRESS|PADDR_1ST_CYCLEPADDR_2ND_CYCLEPADDR_3RD_CYCLEPADDR_4TH_CYCLEPCOLUMN_1ST_CYCLEPCOLUMN_2ND_CYCLEPSTM32F1xx_HAL_SPI_H8 Q "uMode "u Direction "u DataSizeo "u CLKPolarityP "u CLKPhase "uNSS "uBaudRatePrescaler "u FirstBit] "uTIModef "uCRCCalculation1 "uCRCPolynomial~SPI_InitTypeDefSHAL_SPI_STATE_RESETHAL_SPI_STATE_READYHAL_SPI_STATE_BUSY7HAL_SPI_STATE_BUSY_TX&HAL_SPI_STATE_BUSY_RX(!HAL_SPI_STATE_BUSY_TX_RXHAL_SPI_STATE_ERRORHAL_SPI_STATE_ABORTHAL_SPI_StateTypeDef8__SPI_HandleTypeDef "u Instance+ ",uInit "u pTxBuffPtrg "u TxXferSizel "u TxXferCount "u pRxBuffPtri "u RxXferSizen "u RxXferCount "uRxISR "uTxISR "uhdmatx "uhdmarx ""uLock ""uState^ "u ErrorCodeSPI_HandleTypeDefPHAL_SPI_ERROR_NONEPHAL_SPI_ERROR_MODFPHAL_SPI_ERROR_CRCiPHAL_SPI_ERROR_OVRJPHAL_SPI_ERROR_DMAoPHAL_SPI_ERROR_FLAG%PHAL_SPI_ERROR_ABORTPSPI_MODE_SLAVEePSPI_MODE_MASTERPSPI_DIRECTION_2LINES$PSPI_DIRECTION_2LINES_RXONLYRPSPI_DIRECTION_1LINEPSPI_DATASIZE_8BITPSPI_DATASIZE_16BITbPSPI_POLARITY_LOWPSPI_POLARITY_HIGHkPSPI_PHASE_1EDGELPSPI_PHASE_2EDGEKP SPI_NSS_SOFTPSPI_NSS_HARD_INPUTPSPI_NSS_HARD_OUTPUT PSPI_BAUDRATEPRESCALER_2 PSPI_BAUDRATEPRESCALER_4 PSPI_BAUDRATEPRESCALER_8!PSPI_BAUDRATEPRESCALER_16!PSPI_BAUDRATEPRESCALER_32!PSPI_BAUDRATEPRESCALER_64"PSPI_BAUDRATEPRESCALER_128k"PSPI_BAUDRATEPRESCALER_256iPSPI_FIRSTBIT_MSBPSPI_FIRSTBIT_LSBPSPI_TIMODE_DISABLEG#PSPI_CRCCALCULATION_DISABLE"PSPI_CRCCALCULATION_ENABLEAP SPI_IT_TXEP SPI_IT_RXNE1P SPI_IT_ERRPSPI_FLAG_RXNEP SPI_FLAG_TXEP SPI_FLAG_BSYPSPI_FLAG_CRCERR(PSPI_FLAG_MODFP SPI_FLAG_OVRPSPI_FLAG_MASK%P__HAL_SPI_RESET_HANDLE_STATEP__HAL_SPI_ENABLE_ITP__HAL_SPI_DISABLE_ITv P__HAL_SPI_GET_IT_SOURCETP__HAL_SPI_GET_FLAG#P__HAL_SPI_CLEAR_CRCERRFLAG!P__HAL_SPI_CLEAR_MODFFLAGX P__HAL_SPI_CLEAR_OVRFLAGP__HAL_SPI_ENABLEP__HAL_SPI_DISABLExPSPI_INVALID_CRC_ERROR/PSPI_VALID_CRC_ERRORP SPI_1LINE_TXP SPI_1LINE_RXPSPI_RESET_CRCPSPI_CHECK_FLAGPSPI_CHECK_IT_SOURCEP IS_SPI_MODEJPIS_SPI_DIRECTION PIS_SPI_DIRECTION_2LINES)P!IS_SPI_DIRECTION_2LINES_OR_1LINEPIS_SPI_DATASIZEP IS_SPI_CPOLAP IS_SPI_CPHASP IS_SPI_NSS}"PIS_SPI_BAUDRATE_PRESCALER PIS_SPI_FIRST_BITPIS_SPI_TIMODEPIS_SPI_CRC_CALCULATIONPIS_SPI_CRC_POLYNOMIAL PIS_SPI_DMA_HANDLE ,hspiSPI_ISCRCErrorValid ,hspi HAL_SPI_Init ,hspiHAL_SPI_DeInit ,hspiHAL_SPI_MspInit ,hspiHAL_SPI_MspDeInit ,hspi,pData ,Size:, TimeoutHAL_SPI_Transmit ,hspi,pData ,Size:, TimeoutHAL_SPI_Receive ,hspi,pTxData ,pRxData ,Size:, Timeout HAL_SPI_TransmitReceive& ,hspi,pData ,Size:HAL_SPI_Transmit_IT ,hspi,pData ,Size:HAL_SPI_Receive_IT ,hspi,pTxData ,pRxData ,Size:#HAL_SPI_TransmitReceive_IT$ ,hspi,pData ,Size:HAL_SPI_Transmit_DMA ,hspi,pData ,Size:HAL_SPI_Receive_DMAO ,hspi,pTxData ,pRxData ,Size:$HAL_SPI_TransmitReceive_DMA ,hspiHAL_SPI_DMAPausey ,hspiHAL_SPI_DMAResume ,hspiHAL_SPI_DMAStop ,hspiHAL_SPI_AbortW ,hspiHAL_SPI_Abort_ITU ,hspiHAL_SPI_IRQHandler ,hspiHAL_SPI_TxCpltCallback ,hspiHAL_SPI_RxCpltCallback ,hspi!HAL_SPI_TxRxCpltCallback ,hspi#HAL_SPI_TxHalfCpltCallbackN ,hspi#HAL_SPI_RxHalfCpltCallbackP ,hspi%HAL_SPI_TxRxHalfCpltCallback ,hspiHAL_SPI_ErrorCallback( ,hspi"HAL_SPI_AbortCpltCallback ,hspiHAL_SPI_GetState( ,hspiHAL_SPI_GetErrorPSTM32F1xx_HAL_TIM_H8 Q "w Prescaler "w CounterModeP "wPeriod\ "wClockDivision "wRepetitionCounter "wAutoReloadPreloadTIM_Base_InitTypeDefq8 Q "wOCMode "wPulse "w OCPolarity "w OCNPolarityy "w OCFastMode  "w OCIdleState "w OCNIdleStateLTIM_OC_InitTypeDef^8 Q "wOCMode "wPulse "w OCPolarity "w OCNPolarityp "w OCIdleState "w OCNIdleStateC "w ICPolarity "w ICSelectionr "w ICFilter!TIM_OnePulse_InitTypeDef8 Q "w ICPolarity "w ICSelectiong "w ICPrescalerl "w ICFilterTIM_IC_InitTypeDefd8 Q "w EncoderModeN "w IC1Polarity "w IC1Selection. "w IC1Prescaler3 "w IC1Filtert "w IC2Polarity "w IC2Selection- "w IC2Prescaler2 "w IC2Filters TIM_Encoder_InitTypeDef&8 Q "w ClockSource+ "wClockPolarityD "wClockPrescaler "w ClockFilter6TIM_ClockConfigTypeDef8 Q "wClearInputState "wClearInputSource "wClearInputPolarity) "wClearInputPrescaler "wClearInputFilter$TIM_ClearInputConfigTypeDef8 Q "wMasterOutputTrigger "wMasterSlaveMode TIM_MasterConfigTypeDef8 Q "w SlaveMode "w InputTrigger "wTriggerPolarityG "wTriggerPrescaler "wTriggerFilter9TIM_SlaveConfigTypeDef8 Q "wOffStateRunMode "wOffStateIDLEMode "w LockLevel "w DeadTimey "w BreakState "wBreakPolarity3 "w BreakFilter% "wAutomaticOutput0'TIM_BreakDeadTimeConfigTypeDefHAL_TIM_STATE_RESETHAL_TIM_STATE_READYHAL_TIM_STATE_BUSY9HAL_TIM_STATE_TIMEOUTOHAL_TIM_STATE_ERRORHAL_TIM_StateTypeDef!HAL_TIM_ACTIVE_CHANNEL_1!HAL_TIM_ACTIVE_CHANNEL_2!HAL_TIM_ACTIVE_CHANNEL_3!HAL_TIM_ACTIVE_CHANNEL_4'HAL_TIM_ACTIVE_CHANNEL_CLEAREDHAL_TIM_ActiveChannelE8 Q "w Instance "wInit ""wChannel <"whdma ""wLock ""wStatePTIM_HandleTypeDef"PTIM_CLEARINPUTSOURCE_NONE!PTIM_CLEARINPUTSOURCE_ETR@PTIM_DMABASE_CR1RPTIM_DMABASE_CR2QPTIM_DMABASE_SMCRPTIM_DMABASE_DIERPTIM_DMABASE_SRuPTIM_DMABASE_EGR:PTIM_DMABASE_CCMR1PTIM_DMABASE_CCMR2PTIM_DMABASE_CCERPTIM_DMABASE_CNT3PTIM_DMABASE_PSC2PTIM_DMABASE_ARR3PTIM_DMABASE_RCR1PTIM_DMABASE_CCR1 PTIM_DMABASE_CCR2 PTIM_DMABASE_CCR3 PTIM_DMABASE_CCR4 PTIM_DMABASE_BDTRPTIM_DMABASE_DCR?PTIM_DMABASE_DMARPTIM_EVENTSOURCE_UPDATEPTIM_EVENTSOURCE_CC1PTIM_EVENTSOURCE_CC2PTIM_EVENTSOURCE_CC3PTIM_EVENTSOURCE_CC4PTIM_EVENTSOURCE_COM PTIM_EVENTSOURCE_TRIGGERPTIM_EVENTSOURCE_BREAKA(P TIM_INPUTCHANNELPOLARITY_RISING)P!TIM_INPUTCHANNELPOLARITY_FALLING*P"TIM_INPUTCHANNELPOLARITY_BOTHEDGE!PTIM_ETRPOLARITY_INVERTED3$PTIM_ETRPOLARITY_NONINVERTEDBPTIM_ETRPRESCALER_DIV1YPTIM_ETRPRESCALER_DIV2XPTIM_ETRPRESCALER_DIV4VPTIM_ETRPRESCALER_DIV8RPTIM_COUNTERMODE_UPPTIM_COUNTERMODE_DOWN~'PTIM_COUNTERMODE_CENTERALIGNED1'PTIM_COUNTERMODE_CENTERALIGNED2'PTIM_COUNTERMODE_CENTERALIGNED3PTIM_CLOCKDIVISION_DIV1PTIM_CLOCKDIVISION_DIV2PTIM_CLOCKDIVISION_DIV4 PTIM_OUTPUTSTATE_DISABLEPTIM_OUTPUTSTATE_ENABLE'PTIM_AUTORELOAD_PRELOAD_DISABLE&PTIM_AUTORELOAD_PRELOAD_ENABLEPTIM_OCFAST_DISABLEKPTIM_OCFAST_ENABLE!PTIM_OUTPUTNSTATE_DISABLE? PTIM_OUTPUTNSTATE_ENABLEPTIM_OCPOLARITY_HIGHPTIM_OCPOLARITY_LOWPTIM_OCNPOLARITY_HIGHPTIM_OCNPOLARITY_LOWPTIM_OCIDLESTATE_SETPTIM_OCIDLESTATE_RESETEPTIM_OCNIDLESTATE_SETPTIM_OCNIDLESTATE_RESETPTIM_ICPOLARITY_RISING-PTIM_ICPOLARITY_FALLING PTIM_ICPOLARITY_BOTHEDGE!PTIM_ICSELECTION_DIRECTTIi#PTIM_ICSELECTION_INDIRECTTIPTIM_ICSELECTION_TRCPTIM_ICPSC_DIV1PTIM_ICPSC_DIV2PTIM_ICPSC_DIV4~PTIM_ICPSC_DIV8zPTIM_OPMODE_SINGLE{PTIM_OPMODE_REPETITIVE4PTIM_ENCODERMODE_TI1 PTIM_ENCODERMODE_TI2 PTIM_ENCODERMODE_TI12PTIM_IT_UPDATEP TIM_IT_CC1P TIM_IT_CC2P TIM_IT_CC3P TIM_IT_CC4P TIM_IT_COMPTIM_IT_TRIGGERVP TIM_IT_BREAK PTIM_COMMUTATION_TRGIu!PTIM_COMMUTATION_SOFTWARE8PTIM_DMA_UPDATErP TIM_DMA_CC1P TIM_DMA_CC2P TIM_DMA_CC3P TIM_DMA_CC4P TIM_DMA_COM\PTIM_DMA_TRIGGERPTIM_FLAG_UPDATE(P TIM_FLAG_CC1:P TIM_FLAG_CC29P TIM_FLAG_CC38P TIM_FLAG_CC47P TIM_FLAG_COMPTIM_FLAG_TRIGGERPTIM_FLAG_BREAKPTIM_FLAG_CC1OFPTIM_FLAG_CC2OFPTIM_FLAG_CC3OFPTIM_FLAG_CC4OFPTIM_CHANNEL_1PTIM_CHANNEL_2PTIM_CHANNEL_3PTIM_CHANNEL_4PTIM_CHANNEL_ALL3!PTIM_CLOCKSOURCE_ETRMODE2t!PTIM_CLOCKSOURCE_INTERNALYPTIM_CLOCKSOURCE_ITR0PTIM_CLOCKSOURCE_ITR1PTIM_CLOCKSOURCE_ITR2PTIM_CLOCKSOURCE_ITR3PTIM_CLOCKSOURCE_TI1EDePTIM_CLOCKSOURCE_TI1PTIM_CLOCKSOURCE_TI2!PTIM_CLOCKSOURCE_ETRMODE1u#PTIM_CLOCKPOLARITY_INVERTED&PTIM_CLOCKPOLARITY_NONINVERTED!PTIM_CLOCKPOLARITY_RISINGG"PTIM_CLOCKPOLARITY_FALLING#PTIM_CLOCKPOLARITY_BOTHEDGE PTIM_CLOCKPRESCALER_DIV1 PTIM_CLOCKPRESCALER_DIV2 PTIM_CLOCKPRESCALER_DIV4 PTIM_CLOCKPRESCALER_DIV8(P TIM_CLEARINPUTPOLARITY_INVERTED+P#TIM_CLEARINPUTPOLARITY_NONINVERTED(%PTIM_CLEARINPUTPRESCALER_DIV1?%PTIM_CLEARINPUTPRESCALER_DIV2>%PTIM_CLEARINPUTPRESCALER_DIV4<%PTIM_CLEARINPUTPRESCALER_DIV88PTIM_OSSR_ENABLEPTIM_OSSR_DISABLEPTIM_OSSI_ENABLE PTIM_OSSI_DISABLEPTIM_LOCKLEVEL_OFFPTIM_LOCKLEVEL_13PTIM_LOCKLEVEL_22PTIM_LOCKLEVEL_31PTIM_BREAK_ENABLEPTIM_BREAK_DISABLEPTIM_BREAKPOLARITY_LOW.PTIM_BREAKPOLARITY_HIGH$PTIM_AUTOMATICOUTPUT_DISABLEa#PTIM_AUTOMATICOUTPUT_ENABLEPTIM_TRGO_RESETHPTIM_TRGO_ENABLE"PTIM_TRGO_UPDATEP TIM_TRGO_OC1 PTIM_TRGO_OC1REF)PTIM_TRGO_OC2REF(PTIM_TRGO_OC3REF'PTIM_TRGO_OC4REF&#PTIM_MASTERSLAVEMODE_ENABLE$PTIM_MASTERSLAVEMODE_DISABLEPTIM_SLAVEMODE_DISABLEePTIM_SLAVEMODE_RESETPTIM_SLAVEMODE_GATEDPTIM_SLAVEMODE_TRIGGERE PTIM_SLAVEMODE_EXTERNAL1PTIM_OCMODE_TIMINGPTIM_OCMODE_ACTIVEPTIM_OCMODE_INACTIVEPTIM_OCMODE_TOGGLEPTIM_OCMODE_PWM1)PTIM_OCMODE_PWM2(!PTIM_OCMODE_FORCED_ACTIVEn#PTIM_OCMODE_FORCED_INACTIVEP TIM_TS_ITR0GP TIM_TS_ITR1FP TIM_TS_ITR2EP TIM_TS_ITR3DPTIM_TS_TI1F_EDdPTIM_TS_TI1FP1PTIM_TS_TI2FP2P TIM_TS_ETRF5P TIM_TS_NONE6%PTIM_TRIGGERPOLARITY_INVERTED(P TIM_TRIGGERPOLARITY_NONINVERTED#PTIM_TRIGGERPOLARITY_RISING$PTIM_TRIGGERPOLARITY_FALLINGh%PTIM_TRIGGERPOLARITY_BOTHEDGE!"PTIM_TRIGGERPRESCALER_DIV1("PTIM_TRIGGERPRESCALER_DIV2'"PTIM_TRIGGERPRESCALER_DIV4%"PTIM_TRIGGERPRESCALER_DIV8!PTIM_TI1SELECTION_CH1(P TIM_TI1SELECTION_XORCOMBINATIONE%PTIM_DMABURSTLENGTH_1TRANSFER1&PTIM_DMABURSTLENGTH_2TRANSFERS&PTIM_DMABURSTLENGTH_3TRANSFERS&PTIM_DMABURSTLENGTH_4TRANSFERS&PTIM_DMABURSTLENGTH_5TRANSFERS&PTIM_DMABURSTLENGTH_6TRANSFERS&PTIM_DMABURSTLENGTH_7TRANSFERS&PTIM_DMABURSTLENGTH_8TRANSFERS&PTIM_DMABURSTLENGTH_9TRANSFERS'PTIM_DMABURSTLENGTH_10TRANSFERS'PTIM_DMABURSTLENGTH_11TRANSFERS'PTIM_DMABURSTLENGTH_12TRANSFERS'PTIM_DMABURSTLENGTH_13TRANSFERS'PTIM_DMABURSTLENGTH_14TRANSFERS'PTIM_DMABURSTLENGTH_15TRANSFERS'PTIM_DMABURSTLENGTH_16TRANSFERS'PTIM_DMABURSTLENGTH_17TRANSFERS'PTIM_DMABURSTLENGTH_18TRANSFERSPTIM_DMA_ID_UPDATEPTIM_DMA_ID_CC1PTIM_DMA_ID_CC2PTIM_DMA_ID_CC3PTIM_DMA_ID_CC4PTIM_DMA_ID_COMMUTATIONPTIM_DMA_ID_TRIGGER-PTIM_CCx_ENABLEbPTIM_CCx_DISABLEPTIM_CCxN_ENABLEPTIM_CCxN_DISABLE%P__HAL_TIM_RESET_HANDLE_STATEP__HAL_TIM_ENABLEP__HAL_TIM_MOE_ENABLEP__HAL_TIM_DISABLEzP__HAL_TIM_MOE_DISABLE2.P&__HAL_TIM_MOE_DISABLE_UNCONDITIONALLY7P__HAL_TIM_ENABLE_ITP__HAL_TIM_DISABLE_ITxP__HAL_TIM_ENABLE_DMAP__HAL_TIM_DISABLE_DMAAP__HAL_TIM_GET_FLAGP__HAL_TIM_CLEAR_FLAG P__HAL_TIM_GET_IT_SOURCEVP__HAL_TIM_CLEAR_IT 'P__HAL_TIM_IS_TIM_COUNTING_DOWN P__HAL_TIM_SET_PRESCALERvP__HAL_TIM_SET_COUNTERP__HAL_TIM_GET_COUNTER!P__HAL_TIM_SET_AUTORELOAD%!P__HAL_TIM_GET_AUTORELOAD1$P__HAL_TIM_SET_CLOCKDIVISION>$P__HAL_TIM_GET_CLOCKDIVISIONJ"P__HAL_TIM_SET_ICPRESCALER"P__HAL_TIM_GET_ICPRESCALERP__HAL_TIM_SET_COMPAREP__HAL_TIM_GET_COMPARE $P__HAL_TIM_ENABLE_OCxPRELOADC%P__HAL_TIM_DISABLE_OCxPRELOAD!P__HAL_TIM_ENABLE_OCxFAST""P__HAL_TIM_DISABLE_OCxFASTP__HAL_TIM_URS_ENABLEhP__HAL_TIM_URS_DISABLE&P__HAL_TIM_SET_CAPTUREPOLARITYPTIM_CCER_CCxE_MASKPTIM_CCER_CCxNE_MASK!PIS_TIM_CLEARINPUT_SOURCE0PIS_TIM_DMA_BASEPIS_TIM_EVENT_SOURCEPIS_TIM_COUNTER_MODE!PIS_TIM_CLOCKDIVISION_DIVD"PIS_TIM_AUTORELOAD_PRELOADPIS_TIM_FAST_STATEWPIS_TIM_OC_POLARITYPIS_TIM_OCN_POLARITYPIS_TIM_OCIDLE_STATEPIS_TIM_OCNIDLE_STATEPIS_TIM_IC_POLARITYPIS_TIM_IC_SELECTIONPIS_TIM_IC_PRESCALERPIS_TIM_OPM_MODEPIS_TIM_ENCODER_MODEPIS_TIM_DMA_SOURCEcPIS_TIM_CHANNELSPIS_TIM_OPM_CHANNELS&PIS_TIM_COMPLEMENTARY_CHANNELSPIS_TIM_CLOCKSOURCE&PIS_TIM_CLOCKPOLARITYPIS_TIM_CLOCKPRESCALERPPIS_TIM_CLOCKFILTER1#PIS_TIM_CLEARINPUT_POLARITY$PIS_TIM_CLEARINPUT_PRESCALERZ!PIS_TIM_CLEARINPUT_FILTER;PIS_TIM_OSSR_STATE>PIS_TIM_OSSI_STATEGPIS_TIM_LOCK_LEVELePIS_TIM_BREAK_FILTERPIS_TIM_BREAK_STATEPIS_TIM_BREAK_POLARITY%&PIS_TIM_AUTOMATIC_OUTPUT_STATEvPIS_TIM_TRGO_SOURCEPIS_TIM_MSM_STATEPIS_TIM_SLAVE_MODEfPIS_TIM_PWM_MODEPIS_TIM_OC_MODEU!PIS_TIM_TRIGGER_SELECTION>/P'IS_TIM_INTERNAL_TRIGGEREVENT_SELECTIONPIS_TIM_TRIGGERPOLARITY PIS_TIM_TRIGGERPRESCALERPIS_TIM_TRIGGERFILTERPIS_TIM_TI1SELECTIONPIS_TIM_DMA_LENGTHrPIS_TIM_IC_FILTERPIS_TIM_DEADTIME,)P!IS_TIM_SLAVEMODE_TRIGGER_ENABLED!PTIM_SET_ICPRESCALERVALUE]#PTIM_RESET_ICPRESCALERVALUE PTIM_SET_CAPTUREPOLARITY"PTIM_RESET_CAPTUREPOLARITYPSTM32F1xx_HAL_TIM_EX_H8 Q "z IC1Polarity "z IC1Prescaler7 "z IC1Filterx "zCommutation_Delay#TIM_HallSensor_InitTypeDef ,htim,sConfig"HAL_TIMEx_HallSensor_Init ,htim$HAL_TIMEx_HallSensor_DeInit ,htim%HAL_TIMEx_HallSensor_MspInitX ,htim'HAL_TIMEx_HallSensor_MspDeInit ,htim#HAL_TIMEx_HallSensor_Start ,htim"HAL_TIMEx_HallSensor_Stop| ,htim&HAL_TIMEx_HallSensor_Start_IT ,htim%HAL_TIMEx_HallSensor_Stop_ITz ,htim,pData,Lengtho'HAL_TIMEx_HallSensor_Start_DMA ,htim&HAL_TIMEx_HallSensor_Stop_DMAC ,htim, ChannelHAL_TIMEx_OCN_Start; ,htim, ChannelHAL_TIMEx_OCN_Stop ,htim, ChannelHAL_TIMEx_OCN_Start_IT9 ,htim, ChannelHAL_TIMEx_OCN_Stop_IT ,htim, Channel,pData,Lengtho HAL_TIMEx_OCN_Start_DMA ,htim, ChannelHAL_TIMEx_OCN_Stop_DMAl ,htim, ChannelHAL_TIMEx_PWMN_Start ,htim, ChannelHAL_TIMEx_PWMN_StopA ,htim, Channel HAL_TIMEx_PWMN_Start_IT ,htim, ChannelHAL_TIMEx_PWMN_Stop_IT? ,htim, Channel,pData,Lengtho!HAL_TIMEx_PWMN_Start_DMA ,htim, Channel HAL_TIMEx_PWMN_Stop_DMA ,htim, OutputChannel{"HAL_TIMEx_OnePulseN_Start ,htim, OutputChannel{!HAL_TIMEx_OnePulseN_Stop ,htim, OutputChannel{%HAL_TIMEx_OnePulseN_Start_IT ,htim, OutputChannel{$HAL_TIMEx_OnePulseN_Stop_IT ,htim,  InputTrigger, CommutationSource$HAL_TIMEx_ConfigCommutEvent ,htim,  InputTrigger, CommutationSource'HAL_TIMEx_ConfigCommutEvent_IT ,htim,  InputTrigger, CommutationSource( HAL_TIMEx_ConfigCommutEvent_DMAr ,htim,sMasterConfig.&HAL_TIMEx_MasterConfigSynchronizationP ,htim,sBreakDeadTimeConfig&HAL_TIMEx_ConfigBreakDeadTime< ,htim, RemapHAL_TIMEx_RemapConfig9 ,htim!HAL_TIMEx_CommutCallback ,htim)!HAL_TIMEx_CommutHalfCpltCallback ,htim HAL_TIMEx_BreakCallback ,htim&HAL_TIMEx_HallSensor_GetState ,hdma/!TIMEx_DMACommutationCplt ,hdma/%TIMEx_DMACommutationHalfCplt: ,htimHAL_TIM_Base_Init ,htimHAL_TIM_Base_DeInit. ,htimHAL_TIM_Base_MspInit ,htimHAL_TIM_Base_MspDeInit ,htimHAL_TIM_Base_Start_ ,htimHAL_TIM_Base_Stop ,htimHAL_TIM_Base_Start_IT] ,htimHAL_TIM_Base_Stop_IT ,htim,pData,LengthoHAL_TIM_Base_Start_DMA& ,htimHAL_TIM_Base_Stop_DMA ,htimHAL_TIM_OC_Init ,htimHAL_TIM_OC_DeInit ,htimHAL_TIM_OC_MspInit ,htimHAL_TIM_OC_MspDeInit ,htim, ChannelHAL_TIM_OC_StartL ,htim, ChannelHAL_TIM_OC_Stop ,htim, ChannelHAL_TIM_OC_Start_ITJ ,htim, ChannelHAL_TIM_OC_Stop_IT ,htim, Channel,pData,LengthoHAL_TIM_OC_Start_DMA ,htim, ChannelHAL_TIM_OC_Stop_DMA} ,htimHAL_TIM_PWM_Initd ,htimHAL_TIM_PWM_DeInit ,htimHAL_TIM_PWM_MspInit. ,htimHAL_TIM_PWM_MspDeInit ,htim, ChannelHAL_TIM_PWM_Start ,htim, ChannelHAL_TIM_PWM_StopR ,htim, ChannelHAL_TIM_PWM_Start_IT ,htim, ChannelHAL_TIM_PWM_Stop_ITP ,htim, Channel,pData,LengthoHAL_TIM_PWM_Start_DMA ,htim, ChannelHAL_TIM_PWM_Stop_DMA ,htimHAL_TIM_IC_Init ,htimHAL_TIM_IC_DeInit! ,htimHAL_TIM_IC_MspInit ,htimHAL_TIM_IC_MspDeInit ,htim, ChannelHAL_TIM_IC_StartR ,htim, ChannelHAL_TIM_IC_Stop ,htim, ChannelHAL_TIM_IC_Start_ITP ,htim, ChannelHAL_TIM_IC_Stop_IT ,htim, Channel,pData,LengthoHAL_TIM_IC_Start_DMA ,htim, ChannelHAL_TIM_IC_Stop_DMA ,htim,  OnePulseModeHAL_TIM_OnePulse_Init# ,htim HAL_TIM_OnePulse_DeInitv ,htim!HAL_TIM_OnePulse_MspInit ,htim#HAL_TIM_OnePulse_MspDeInit@ ,htim, OutputChannel{HAL_TIM_OnePulse_Start ,htim, OutputChannel{HAL_TIM_OnePulse_Stop ,htim, OutputChannel{"HAL_TIM_OnePulse_Start_IT ,htim, OutputChannel{!HAL_TIM_OnePulse_Stop_IT ,htim,sConfigHAL_TIM_Encoder_Init ,htimHAL_TIM_Encoder_DeInit ,htim HAL_TIM_Encoder_MspInitZ ,htim"HAL_TIM_Encoder_MspDeInit ,htim, ChannelHAL_TIM_Encoder_Start ,htim, ChannelHAL_TIM_Encoder_Stop~ ,htim, Channel!HAL_TIM_Encoder_Start_IT ,htim, Channel HAL_TIM_Encoder_Stop_IT| ,htim, Channel,pData1,pData2,Lengtho"HAL_TIM_Encoder_Start_DMA ,htim, Channel!HAL_TIM_Encoder_Stop_DMAE ,htimHAL_TIM_IRQHandler ,htim,sConfig, Channel!HAL_TIM_OC_ConfigChannel; ,htim,sConfig, Channel"HAL_TIM_PWM_ConfigChannel ,htim,sConfig, Channel!HAL_TIM_IC_ConfigChannelA ,htim,sConfig, OutputChannel{,  InputChannel'HAL_TIM_OnePulse_ConfigChannel ,htim,sClearInputConfig, Channel!HAL_TIM_ConfigOCrefClear/ ,htim,sClockSourceConfig"HAL_TIM_ConfigClockSource ,htim, TI1_SelectionHAL_TIM_ConfigTI1Input ,htim, sSlaveConfig#HAL_TIM_SlaveConfigSynchro ,htim, sSlaveConfig&HAL_TIM_SlaveConfigSynchro_IT ,htim, BurstBaseAddressn, BurstRequestSrc, BurstBufferQ,  BurstLengthW$HAL_TIM_DMABurst_WriteStart ,htim, BurstRequestSrc#HAL_TIM_DMABurst_WriteStopE ,htim, BurstBaseAddressn, BurstRequestSrc, BurstBufferQ,  BurstLengthW#HAL_TIM_DMABurst_ReadStartl ,htim, BurstRequestSrc"HAL_TIM_DMABurst_ReadStop ,htim,  EventSourceVHAL_TIM_GenerateEvent ,htim, Channel"HAL_TIM_ReadCapturedValue ,htim&HAL_TIM_PeriodElapsedCallback ,htim.&HAL_TIM_PeriodElapsedHalfCpltCallback ,htim( HAL_TIM_OC_DelayElapsedCallback ,htim#HAL_TIM_IC_CaptureCallbackk ,htim+#HAL_TIM_IC_CaptureHalfCpltCallbackM ,htim*"HAL_TIM_PWM_PulseFinishedCallback ,htim2*HAL_TIM_PWM_PulseFinishedHalfCpltCallbackx ,htim HAL_TIM_TriggerCallback\ ,htim( HAL_TIM_TriggerHalfCpltCallback> ,htimHAL_TIM_ErrorCallback* ,htimHAL_TIM_Base_GetStateF ,htimHAL_TIM_OC_GetState3 ,htimHAL_TIM_PWM_GetState ,htimHAL_TIM_IC_GetState9 ,htim"HAL_TIM_OnePulse_GetState ,htim!HAL_TIM_Encoder_GetState ,TIMxg, StructureTIM_Base_SetConfig ,TIMxg, TIM_ICPolarity, TIM_ICSelectionF,  TIM_ICFilterTIM_TI1_SetConfig ,TIMxg, OC_ConfigxTIM_OC2_SetConfig ,TIMxg, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity,  ExtTRGFilterCTIM_ETR_SetConfig ,hdma/TIM_DMADelayPulseCplt ,hdma/"TIM_DMADelayPulseHalfCplt ,hdma/ TIM_DMAError ,hdma/TIM_DMACaptureCpltB ,hdma/TIM_DMACaptureHalfCplt ,TIMxg, Channel,  ChannelState TIM_CCxChannelCmdP__STM32F1xx_HAL_UART_H8 Q "} BaudRate "} WordLength "} StopBitsY "}Parity "}Mode "} HwFlowCtl "} OverSamplingUART_InitTypeDefHAL_UART_STATE_RESETHAL_UART_STATE_READYHAL_UART_STATE_BUSYHAL_UART_STATE_BUSY_TXHAL_UART_STATE_BUSY_RX"HAL_UART_STATE_BUSY_TX_RXHAL_UART_STATE_TIMEOUTHAL_UART_STATE_ERRORHAL_UART_StateTypeDefV8__UART_HandleTypeDefG "} Instance< "}Init "} pTxBuffPtrx "} TxXferSize} "} TxXferCount  "} pRxBuffPtrz "} RxXferSize "} RxXferCount "}hdmatx "}hdmarx ""}Lock ""}gState ""}RxState "} ErrorCodeUART_HandleTypeDefEPHAL_UART_ERROR_NONEPHAL_UART_ERROR_PE\PHAL_UART_ERROR_NE^PHAL_UART_ERROR_FEfPHAL_UART_ERROR_ORE PHAL_UART_ERROR_DMAPUART_WORDLENGTH_8B5PUART_WORDLENGTH_9B4PUART_STOPBITS_1 PUART_STOPBITS_2 PUART_PARITY_NONEPUART_PARITY_EVENPUART_PARITY_ODDPUART_HWCONTROL_NONEPUART_HWCONTROL_RTSPUART_HWCONTROL_CTSPUART_HWCONTROL_RTS_CTSP UART_MODE_RXP UART_MODE_TXPUART_MODE_TX_RXPUART_STATE_DISABLE8PUART_STATE_ENABLEPUART_OVERSAMPLING_16&PUART_LINBREAKDETECTLENGTH_10B1&PUART_LINBREAKDETECTLENGTH_11B0#PUART_WAKEUPMETHOD_IDLELINE&PUART_WAKEUPMETHOD_ADDRESSMARKPUART_FLAG_CTSPUART_FLAG_LBDPUART_FLAG_TXEP UART_FLAG_TCPUART_FLAG_RXNE^PUART_FLAG_IDLE}PUART_FLAG_OREP UART_FLAG_NE P UART_FLAG_FEP UART_FLAG_PE P UART_IT_PEP UART_IT_TXE-P UART_IT_TCP UART_IT_RXNEP UART_IT_IDLEP UART_IT_LBDLP UART_IT_CTS4P UART_IT_ERR5&P__HAL_UART_RESET_HANDLE_STATE$P__HAL_UART_FLUSH_DRREGISTER,P__HAL_UART_GET_FLAGP__HAL_UART_CLEAR_FLAG4 P__HAL_UART_CLEAR_PEFLAG P__HAL_UART_CLEAR_FEFLAG P__HAL_UART_CLEAR_NEFLAG!P__HAL_UART_CLEAR_OREFLAGH"P__HAL_UART_CLEAR_IDLEFLAGP__HAL_UART_ENABLE_ITsP__HAL_UART_DISABLE_IT$!P__HAL_UART_GET_IT_SOURCE(P __HAL_UART_HWCONTROL_CTS_ENABLE)P!__HAL_UART_HWCONTROL_CTS_DISABLE(P __HAL_UART_HWCONTROL_RTS_ENABLE)P!__HAL_UART_HWCONTROL_RTS_DISABLEP__HAL_UART_ENABLEuP__HAL_UART_DISABLE&,huartHAL_UART_Initk,huartHAL_HalfDuplex_Init,huart, BreakDetectLength HAL_LIN_Init,huart,Address,  WakeUpMethod HAL_MultiProcessor_Init,huartHAL_UART_DeInit,huartHAL_UART_MspInit5,huartHAL_UART_MspDeInit,huart,pData ,Size:, TimeoutHAL_UART_Transmit,huart,pData ,Size:, TimeoutHAL_UART_Receive6,huart,pData ,Size:HAL_UART_Transmit_IT,huart,pData ,Size:HAL_UART_Receive_IT4,huart,pData ,Size:HAL_UART_Transmit_DMAl,huart,pData ,Size:HAL_UART_Receive_DMA,huartHAL_UART_DMAPause',huartHAL_UART_DMAResume,huartHAL_UART_DMAStop,huartHAL_UART_Abort,huartHAL_UART_AbortTransmit,huartHAL_UART_AbortReceive4,huartHAL_UART_Abort_IT,huart"HAL_UART_AbortTransmit_IT,huart!HAL_UART_AbortReceive_IT2,huartHAL_UART_IRQHandlerI,huart HAL_UART_TxCpltCallback,huart$HAL_UART_TxHalfCpltCallback,huart HAL_UART_RxCpltCallback,huart$HAL_UART_RxHalfCpltCallback,huartHAL_UART_ErrorCallback,huart#HAL_UART_AbortCpltCallbackM,huart+#HAL_UART_AbortTransmitCpltCallback,huart*"HAL_UART_AbortReceiveCpltCallback|,huartHAL_LIN_SendBreak,huart)!HAL_MultiProcessor_EnterMuteMode,,huart( HAL_MultiProcessor_ExitMuteMode,huart)!HAL_HalfDuplex_EnableTransmitterD,huart&HAL_HalfDuplex_EnableReceiver,huartHAL_UART_GetState,huartHAL_UART_GetErrorP UART_IT_MASKPUART_CR1_REG_INDEX2PUART_CR2_REG_INDEX1PUART_CR3_REG_INDEX0PIS_UART_WORD_LENGTH PIS_UART_LIN_WORD_LENGTHhPIS_UART_STOPBITSPIS_UART_PARITY@&PIS_UART_HARDWARE_FLOW_CONTROLP IS_UART_MODEPIS_UART_STATE!PIS_UART_LIN_OVERSAMPLING,(P IS_UART_LIN_BREAK_DETECT_LENGTHPIS_UART_WAKEUPMETHODPIS_UART_BAUDRATEPIS_UART_ADDRESSPUART_DIV_SAMPLING16 PUART_DIVMANT_SAMPLING16 PUART_DIVFRAQ_SAMPLING16PUART_BRR_SAMPLING16PUART_DIV_SAMPLING87PUART_DIVMANT_SAMPLING8PUART_DIVFRAQ_SAMPLING8PUART_BRR_SAMPLING84 P__STM32F1xx_HAL_USART_HV8 Q " BaudRate " WordLength " StopBits "ParityC "Mode; " CLKPolarity " CLKPhase " CLKLastBit'USART_InitTypeDefHAL_USART_STATE_RESETNHAL_USART_STATE_READY\HAL_USART_STATE_BUSY HAL_USART_STATE_BUSY_TX HAL_USART_STATE_BUSY_RX#HAL_USART_STATE_BUSY_TX_RXp HAL_USART_STATE_TIMEOUTHAL_USART_STATE_ERRORGHAL_USART_StateTypeDef8__USART_HandleTypeDef " Instanceb " Init " pTxBuffPtr " TxXferSize " TxXferCount3 " pRxBuffPtr " RxXferSize " RxXferCount5 "hdmatx "hdmarx ""Lock ""State " ErrorCodeUSART_HandleTypeDefPHAL_USART_ERROR_NONEhPHAL_USART_ERROR_PEPHAL_USART_ERROR_NE PHAL_USART_ERROR_FEPHAL_USART_ERROR_OREPHAL_USART_ERROR_DMAPUSART_WORDLENGTH_8BPUSART_WORDLENGTH_9BPUSART_STOPBITS_1PUSART_STOPBITS_0_5PUSART_STOPBITS_2PUSART_STOPBITS_1_5PUSART_PARITY_NONESPUSART_PARITY_EVENUPUSART_PARITY_ODDPUSART_MODE_RXPUSART_MODE_TXPUSART_MODE_TX_RXPUSART_CLOCK_DISABLEPUSART_CLOCK_ENABLEGPUSART_POLARITY_LOWPUSART_POLARITY_HIGHPUSART_PHASE_1EDGEPUSART_PHASE_2EDGEPUSART_LASTBIT_DISABLEMPUSART_LASTBIT_ENABLEPUSART_NACK_ENABLEPUSART_NACK_DISABLEIPUSART_FLAG_TXEWPUSART_FLAG_TCPUSART_FLAG_RXNE PUSART_FLAG_IDLE(PUSART_FLAG_OREbPUSART_FLAG_NEPUSART_FLAG_FEPUSART_FLAG_PEP USART_IT_PE6P USART_IT_TXEP USART_IT_TC4PUSART_IT_RXNEPUSART_IT_IDLEP USART_IT_ERR'P__HAL_USART_RESET_HANDLE_STATEAP__HAL_USART_GET_FLAGjP__HAL_USART_CLEAR_FLAG!P__HAL_USART_CLEAR_PEFLAGF!P__HAL_USART_CLEAR_FEFLAGP!P__HAL_USART_CLEAR_NEFLAGH"P__HAL_USART_CLEAR_OREFLAG#P__HAL_USART_CLEAR_IDLEFLAGP__HAL_USART_ENABLE_ITP__HAL_USART_DISABLE_IT"P__HAL_USART_GET_IT_SOURCE*P"__HAL_USART_ONE_BIT_SAMPLE_ENABLEb+P#__HAL_USART_ONE_BIT_SAMPLE_DISABLEP__HAL_USART_ENABLE P__HAL_USART_DISABLE,husart.HAL_USART_Init,husart.HAL_USART_DeIniti,husart.HAL_USART_MspInit,husart.HAL_USART_MspDeInit3,husart.,pTxData ,Size:, TimeoutHAL_USART_TransmitP,husart.,pRxData ,Size:, TimeoutHAL_USART_Receive,husart.,pTxData ,pRxData ,Size:, Timeout"HAL_USART_TransmitReceive,husart.,pTxData ,Size:HAL_USART_Transmit_ITN,husart.,pRxData ,Size:HAL_USART_Receive_IT,husart.,pTxData ,pRxData ,Size:%HAL_USART_TransmitReceive_IT},husart.,pTxData ,Size:HAL_USART_Transmit_DMA,husart.,pRxData ,Size:HAL_USART_Receive_DMA,husart.,pTxData ,pRxData ,Size:&HAL_USART_TransmitReceive_DMAF,husart.HAL_USART_DMAPause,husart.HAL_USART_DMAResume],husart.HAL_USART_DMAStop,,husart.HAL_USART_Abort,husart.HAL_USART_Abort_IT,husart.HAL_USART_IRQHandler,husart.!HAL_USART_TxCpltCallback*,husart.%HAL_USART_TxHalfCpltCallback,husart.!HAL_USART_RxCpltCallback,,husart.%HAL_USART_RxHalfCpltCallback,husart.#HAL_USART_TxRxCpltCallback\,husart. HAL_USART_ErrorCallback,husart.$HAL_USART_AbortCpltCallback,husart.HAL_USART_GetState,husart.HAL_USART_GetErrorxPUSART_IT_MASKPUSART_CR1_REG_INDEXPUSART_CR2_REG_INDEXPUSART_CR3_REG_INDEXPIS_USART_NACK_STATEPIS_USART_LASTBITPIS_USART_PHASEUPIS_USART_POLARITYLPIS_USART_CLOCKZPIS_USART_WORD_LENGTH]PIS_USART_STOPBITSHPIS_USART_PARITYPIS_USART_MODEPIS_USART_BAUDRATExP USART_DIVPUSART_DIVMANTPUSART_DIVFRAQP USART_BRRP__STM32F1xx_HAL_IRDA_H8 Q " BaudRateo " WordLengthu "Parity "Mode " Prescaler " IrDAModeIRDA_InitTypeDefHAL_IRDA_STATE_RESETHAL_IRDA_STATE_READYHAL_IRDA_STATE_BUSYHAL_IRDA_STATE_BUSY_TXHAL_IRDA_STATE_BUSY_RX"HAL_IRDA_STATE_BUSY_TX_RXHAL_IRDA_STATE_TIMEOUTHAL_IRDA_STATE_ERRORHAL_IRDA_StateTypeDefr8 Q "р Instance# "рInit "р pTxBuffPtr_ "р TxXferSized "р TxXferCount "р pRxBuffPtra "р RxXferSizef "р RxXferCount "рhdmatx "рhdmarx ""рLock ""рgState ""рRxState "р ErrorCodeIRDA_HandleTypeDefaPHAL_IRDA_ERROR_NONEPHAL_IRDA_ERROR_PExPHAL_IRDA_ERROR_NEzPHAL_IRDA_ERROR_FEPHAL_IRDA_ERROR_ORE%PHAL_IRDA_ERROR_DMA9PIRDA_WORDLENGTH_8BQPIRDA_WORDLENGTH_9BPPIRDA_PARITY_NONEPIRDA_PARITY_EVENPIRDA_PARITY_ODDP IRDA_MODE_RXP IRDA_MODE_TXPIRDA_MODE_TX_RX PIRDA_POWERMODE_LOWPOWERPIRDA_POWERMODE_NORMALHPIRDA_FLAG_TXEP IRDA_FLAG_TC$PIRDA_FLAG_RXNEzPIRDA_FLAG_IDLEPIRDA_FLAG_OREP IRDA_FLAG_NE(P IRDA_FLAG_FE0P IRDA_FLAG_PE&P IRDA_IT_PEP IRDA_IT_TXEIP IRDA_IT_TCP IRDA_IT_RXNEP IRDA_IT_IDLEP IRDA_IT_LBDhP IRDA_IT_CTSPP IRDA_IT_ERRQ&P__HAL_IRDA_RESET_HANDLE_STATE$P__HAL_IRDA_FLUSH_DRREGISTERHP__HAL_IRDA_GET_FLAGP__HAL_IRDA_CLEAR_FLAGP P__HAL_IRDA_CLEAR_PEFLAG P__HAL_IRDA_CLEAR_FEFLAG P__HAL_IRDA_CLEAR_NEFLAG!P__HAL_IRDA_CLEAR_OREFLAGd"P__HAL_IRDA_CLEAR_IDLEFLAG*P__HAL_IRDA_ENABLE_ITP__HAL_IRDA_DISABLE_IT@!P__HAL_IRDA_GET_IT_SOURCEP__HAL_IRDA_ENABLEP__HAL_IRDA_DISABLEB,hirdaHAL_IRDA_Init,hirdaHAL_IRDA_DeInit,hirdaHAL_IRDA_MspInitQ,hirdaHAL_IRDA_MspDeInit,hirda,pData ,Size:, TimeoutHAL_IRDA_Transmit,hirda,pData ,Size:, TimeoutHAL_IRDA_ReceiveR,hirda,pData ,Size:HAL_IRDA_Transmit_IT,hirda,pData ,Size:HAL_IRDA_Receive_ITP,hirda,pData ,Size:HAL_IRDA_Transmit_DMA,hirda,pData ,Size:HAL_IRDA_Receive_DMA,hirdaHAL_IRDA_DMAPauseC,hirdaHAL_IRDA_DMAResume,hirdaHAL_IRDA_DMAStop,hirdaHAL_IRDA_Abort!,hirdaHAL_IRDA_AbortTransmit,hirdaHAL_IRDA_AbortReceiveP,hirdaHAL_IRDA_Abort_IT,hirda"HAL_IRDA_AbortTransmit_IT,hirda!HAL_IRDA_AbortReceive_ITN,hirdaHAL_IRDA_IRQHandlere,hirda HAL_IRDA_TxCpltCallback,hirda HAL_IRDA_RxCpltCallback,hirda$HAL_IRDA_TxHalfCpltCallback,hirda$HAL_IRDA_RxHalfCpltCallback,hirdaHAL_IRDA_ErrorCallback,hirda#HAL_IRDA_AbortCpltCallbacki,hirda+#HAL_IRDA_AbortTransmitCpltCallback,hirda*"HAL_IRDA_AbortReceiveCpltCallback,hirdaHAL_IRDA_GetState,hirdaHAL_IRDA_GetErrorP IRDA_IT_MASK PIRDA_CR1_REG_INDEXNPIRDA_CR2_REG_INDEXMPIRDA_CR3_REG_INDEXLPIS_IRDA_WORD_LENGTHPIS_IRDA_PARITY\P IS_IRDA_MODEPIS_IRDA_POWERMODE}PIS_IRDA_BAUDRATEP IRDA_DIVYP IRDA_DIVMANT!P IRDA_DIVFRAQ'P IRDA_BRRV$P__STM32F1xx_HAL_SMARTCARD_H<8 Q " BaudRateG " WordLengthM " StopBits "Parity "Mode " CLKPolarity " CLKPhase " CLKLastBit " Prescaler " GuardTime " NACKState/SMARTCARD_InitTypeDef"HAL_SMARTCARD_STATE_RESET4"HAL_SMARTCARD_STATE_READYB!HAL_SMARTCARD_STATE_BUSYv$HAL_SMARTCARD_STATE_BUSY_TXe$HAL_SMARTCARD_STATE_BUSY_RXg'HAL_SMARTCARD_STATE_BUSY_TX_RXV$HAL_SMARTCARD_STATE_TIMEOUT"HAL_SMARTCARD_STATE_ERROR-#HAL_SMARTCARD_StateTypeDef"8__SMARTCARD_HandleTypeDef " Instance ",Inits " pTxBuffPtr2 " TxXferSize7 " TxXferCount " pRxBuffPtr4 " RxXferSize9 " RxXferCount "hdmatx "hdmarx ""Lock ""gState ""RxState[ " ErrorCode SMARTCARD_HandleTypeDef!PHAL_SMARTCARD_ERROR_NONENPHAL_SMARTCARD_ERROR_PEPHAL_SMARTCARD_ERROR_NEPHAL_SMARTCARD_ERROR_FE PHAL_SMARTCARD_ERROR_ORE PHAL_SMARTCARD_ERROR_DMA PSMARTCARD_WORDLENGTH_9BPSMARTCARD_STOPBITS_0_5PSMARTCARD_STOPBITS_1_5PSMARTCARD_PARITY_EVEN;PSMARTCARD_PARITY_ODDPSMARTCARD_MODE_RX{PSMARTCARD_MODE_TXyPSMARTCARD_MODE_TX_RXjPSMARTCARD_POLARITY_LOW PSMARTCARD_POLARITY_HIGHPSMARTCARD_PHASE_1EDGEPSMARTCARD_PHASE_2EDGE"PSMARTCARD_LASTBIT_DISABLE3!PSMARTCARD_LASTBIT_ENABLEPSMARTCARD_NACK_ENABLE~PSMARTCARD_NACK_DISABLE/PSMARTCARD_DMAREQ_TXPSMARTCARD_DMAREQ_RX(P SMARTCARD_PRESCALER_SYSCLK_DIV2@(P SMARTCARD_PRESCALER_SYSCLK_DIV4>(P SMARTCARD_PRESCALER_SYSCLK_DIV6<(P SMARTCARD_PRESCALER_SYSCLK_DIV8:)P!SMARTCARD_PRESCALER_SYSCLK_DIV10)P!SMARTCARD_PRESCALER_SYSCLK_DIV12 )P!SMARTCARD_PRESCALER_SYSCLK_DIV14 )P!SMARTCARD_PRESCALER_SYSCLK_DIV16 )P!SMARTCARD_PRESCALER_SYSCLK_DIV18)P!SMARTCARD_PRESCALER_SYSCLK_DIV20)P!SMARTCARD_PRESCALER_SYSCLK_DIV22 )P!SMARTCARD_PRESCALER_SYSCLK_DIV24 )P!SMARTCARD_PRESCALER_SYSCLK_DIV26)P!SMARTCARD_PRESCALER_SYSCLK_DIV28)P!SMARTCARD_PRESCALER_SYSCLK_DIV30 )P!SMARTCARD_PRESCALER_SYSCLK_DIV32 )P!SMARTCARD_PRESCALER_SYSCLK_DIV34 )P!SMARTCARD_PRESCALER_SYSCLK_DIV36)P!SMARTCARD_PRESCALER_SYSCLK_DIV38)P!SMARTCARD_PRESCALER_SYSCLK_DIV40 )P!SMARTCARD_PRESCALER_SYSCLK_DIV42 )P!SMARTCARD_PRESCALER_SYSCLK_DIV44)P!SMARTCARD_PRESCALER_SYSCLK_DIV46)P!SMARTCARD_PRESCALER_SYSCLK_DIV48)P!SMARTCARD_PRESCALER_SYSCLK_DIV50 )P!SMARTCARD_PRESCALER_SYSCLK_DIV52 )P!SMARTCARD_PRESCALER_SYSCLK_DIV54)P!SMARTCARD_PRESCALER_SYSCLK_DIV56)P!SMARTCARD_PRESCALER_SYSCLK_DIV58)P!SMARTCARD_PRESCALER_SYSCLK_DIV60 )P!SMARTCARD_PRESCALER_SYSCLK_DIV62PSMARTCARD_FLAG_TXE=PSMARTCARD_FLAG_TCPSMARTCARD_FLAG_RXNEPSMARTCARD_FLAG_IDLEPSMARTCARD_FLAG_OREHPSMARTCARD_FLAG_NEPSMARTCARD_FLAG_FEPSMARTCARD_FLAG_PEPSMARTCARD_IT_PEPSMARTCARD_IT_TXEPSMARTCARD_IT_TCPSMARTCARD_IT_RXNEpPSMARTCARD_IT_IDLEPSMARTCARD_IT_ERR+P#__HAL_SMARTCARD_RESET_HANDLE_STATE')P!__HAL_SMARTCARD_FLUSH_DRREGISTER!P__HAL_SMARTCARD_GET_FLAGP#P__HAL_SMARTCARD_CLEAR_FLAG%P__HAL_SMARTCARD_CLEAR_PEFLAG,%P__HAL_SMARTCARD_CLEAR_FEFLAG6%P__HAL_SMARTCARD_CLEAR_NEFLAG.&P__HAL_SMARTCARD_CLEAR_OREFLAG'P__HAL_SMARTCARD_CLEAR_IDLEFLAG"P__HAL_SMARTCARD_ENABLE_IT#P__HAL_SMARTCARD_DISABLE_IT&P__HAL_SMARTCARD_GET_IT_SOURCEP__HAL_SMARTCARD_ENABLE P__HAL_SMARTCARD_DISABLE+P#__HAL_SMARTCARD_DMA_REQUEST_ENABLE5,P$__HAL_SMARTCARD_DMA_REQUEST_DISABLE ,hscHAL_SMARTCARD_Init ,hscHAL_SMARTCARD_ReInitA ,hscHAL_SMARTCARD_DeInitO ,hscHAL_SMARTCARD_MspInit ,hsc HAL_SMARTCARD_MspDeInit ,hsc,pData ,Size:, TimeoutHAL_SMARTCARD_Transmit6 ,hsc,pData ,Size:, TimeoutHAL_SMARTCARD_Receive ,hsc,pData ,Size:"HAL_SMARTCARD_Transmit_IT4 ,hsc,pData ,Size:!HAL_SMARTCARD_Receive_IT ,hsc,pData ,Size:#HAL_SMARTCARD_Transmit_DMA ,hsc,pData ,Size:"HAL_SMARTCARD_Receive_DMA ,hscHAL_SMARTCARD_Abort ,hsc$HAL_SMARTCARD_AbortTransmit4 ,hsc#HAL_SMARTCARD_AbortReceive ,hscHAL_SMARTCARD_Abort_IT ,hsc'HAL_SMARTCARD_AbortTransmit_IT2 ,hsc&HAL_SMARTCARD_AbortReceive_IT ,hsc!HAL_SMARTCARD_IRQHandler ,hsc%HAL_SMARTCARD_TxCpltCallback ,hsc%HAL_SMARTCARD_RxCpltCallback ,hsc$HAL_SMARTCARD_ErrorCallbackg ,hsc( HAL_SMARTCARD_AbortCpltCallback ,hsc0(HAL_SMARTCARD_AbortTransmitCpltCallback| ,hsc/'HAL_SMARTCARD_AbortReceiveCpltCallback ,hscHAL_SMARTCARD_GetStateg ,hscHAL_SMARTCARD_GetError^PSMARTCARD_IT_MASK PSMARTCARD_CR1_REG_INDEX PSMARTCARD_CR3_REG_INDEX!PIS_SMARTCARD_WORD_LENGTHCPIS_SMARTCARD_STOPBITS.PIS_SMARTCARD_PARITYPIS_SMARTCARD_MODEPIS_SMARTCARD_POLARITY2PIS_SMARTCARD_PHASE;PIS_SMARTCARD_LASTBIT PIS_SMARTCARD_NACK_STATEPIS_SMARTCARD_BAUDRATE^PSMARTCARD_DIVPSMARTCARD_DIVMANTPSMARTCARD_DIVFRAQPSMARTCARD_BRRPSTM32F1xx_HAL_WWDG_Hp8 Q " Prescaler "Window  "Counter "EWIModeWWDG_InitTypeDef8 Q " Instance6 "InitWWDG_HandleTypeDefHP WWDG_IT_EWI<PWWDG_FLAG_EWIFsPWWDG_PRESCALER_1PWWDG_PRESCALER_2PWWDG_PRESCALER_4PWWDG_PRESCALER_8PWWDG_EWI_DISABLEPWWDG_EWI_ENABLE*PIS_WWDG_PRESCALERuPIS_WWDG_WINDOWDPIS_WWDG_COUNTERPIS_WWDG_EWI_MODEP__HAL_WWDG_ENABLExP__HAL_WWDG_ENABLE_ITvP__HAL_WWDG_GET_ITCP__HAL_WWDG_CLEAR_ITP__HAL_WWDG_GET_FLAGP__HAL_WWDG_CLEAR_FLAG7!P__HAL_WWDG_GET_IT_SOURCE,hwwdgHAL_WWDG_Initn,hwwdgHAL_WWDG_MspInit8,hwwdgHAL_WWDG_Refresh-,hwwdgHAL_WWDG_IRQHandlerL,hwwdg%HAL_WWDG_EarlyWakeupCallbackmPSTM32F1xx_HAL_PCD_HPSTM32F1xx_LL_USB_HUSB_DEVICE_MODEbUSB_ModeTypeDefd8 Q "dev_endpoints "speedI "ep0_mps " phy_itface4 " Sof_enableb "low_power_enable " lpm_enableA# "battery_charging_enableUSB_CfgTypeDef8 Q "num  "is_inE " is_stall "type "data_pid_start " pmaadress " pmaaddr0? " pmaaddr1> " doublebufferT " tx_fifo_num " maxpacket " xfer_buff " xfer_len " xfer_count USB_EPTypeDefXPDEP0CTL_MPS_64PDEP0CTL_MPS_32PDEP0CTL_MPS_16PDEP0CTL_MPS_8P EP_TYPE_CTRLP EP_TYPE_ISOCP EP_TYPE_BULKP EP_TYPE_INTRP EP_TYPE_MSK5PUSBD_FS_SPEEDPBTABLE_ADDRESSP PMA_ACCESSP EP_ADDR_MSK\ ,USBxg , cfg{ USB_CoreInitj ,USBxg , cfg{ USB_DevInit ,USBxgUSB_EnableGlobalInt ,USBxgUSB_DisableGlobalIntG ,USBxg ,"modeUSB_SetCurrentMode ,USBxg,speedUSB_SetDevSpeedE ,USBxgUSB_FlushRxFifo1 ,USBxg , numUSB_FlushTxFifo/ ,USBxg ,epUSB_ActivateEndpoint ,USBxg ,epUSB_DeactivateEndpoint8 ,USBxg ,epUSB_EPStartXferI ,USBxg ,src, ch_ep_num& ,lenUSB_WritePacket ,USBxg ,dest ,lenUSB_ReadPacket ,USBxg ,epUSB_EPSetStall ,USBxg ,epUSB_EPClearStall ,USBxg,addressUSB_SetDevAddressl ,USBxgUSB_DevConnect ,USBxgUSB_DevDisconnectT ,USBxgUSB_StopDevice ,USBxg,psetup$USB_EP0_OutStart ,USBxgUSB_ReadInterrupts ,USBxg%USB_ReadDevAllOutEpInterrupt ,USBxg,epnum"USB_ReadDevOutEPInterrupt8 ,USBxg$USB_ReadDevAllInEpInterrupt| ,USBxg,epnum!USB_ReadDevInEPInterrupt ,USBxg,  interruptUSB_ClearInterruptsR ,USBxg!USB_ActivateRemoteWakeupe ,USBxg#USB_DeActivateRemoteWakeup ,USBxg, pbUsrBuf, wPMABufAddr,wNBytes USB_WritePMA ,USBxg, pbUsrBuf, wPMABufAddr,wNBytes USB_ReadPMA/HAL_PCD_STATE_RESET HAL_PCD_STATE_READYHAL_PCD_STATE_ERRORHAL_PCD_STATE_BUSYLHAL_PCD_STATE_TIMEOUTbPCD_StateTypeDefLPM_L0-LPM_L1,LPM_L2+LPM_L3*PCD_LPM_StateTypeDefPCD_LPM_L0_ACTIVEPCD_LPM_L1_ACTIVEPCD_LPM_MsgTypeDefPCD_BCD_ERROR"PCD_BCD_CONTACT_DETECTIONc$PCD_BCD_STD_DOWNSTREAM_PORTw)!PCD_BCD_CHARGING_DOWNSTREAM_PORT( PCD_BCD_DEDICATED_CHARGING_PORT$PCD_BCD_DISCOVERY_COMPLETEDPCD_BCD_MsgTypeDef PCD_TypeDefPCD_InitTypeDefhPCD_EPTypeDefk8 Q " Instance " Init " USB_Address0 <"IN_ep <"OUT_epe ""Lock ""State. " ErrorCode <"0Setup "" LPM_State "BESL  "pDataLPCD_HandleTypeDefPSTM32F1xx_HAL_PCD_EX_H ,hpcd*,ep_addr,ep_kind,  pmaadress HAL_PCDEx_PMAConfigg ,hpcd*,state%HAL_PCDEx_SetConnectionStateL ,hpcd* ,"msg}HAL_PCDEx_LPM_Callback@ ,hpcd* ,"msg}HAL_PCDEx_BCD_Callback`PPCD_SPEED_FULLvP PCD_PHY_ULPIPPCD_PHY_EMBEDDEDP PCD_PHY_UTMIP__HAL_PCD_ENABLEP__HAL_PCD_DISABLEP__HAL_PCD_GET_FLAG&P__HAL_PCD_CLEAR_FLAG(P __HAL_USB_WAKEUP_EXTI_ENABLE_IT)P!__HAL_USB_WAKEUP_EXTI_DISABLE_IT'P__HAL_USB_WAKEUP_EXTI_GET_FLAG6)P!__HAL_USB_WAKEUP_EXTI_CLEAR_FLAG1P)__HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE5 ,hpcd* HAL_PCD_Init ,hpcd*HAL_PCD_DeInit% ,hpcd*HAL_PCD_MspInit ,hpcd*HAL_PCD_MspDeInit ,hpcd*HAL_PCD_StartV ,hpcd* HAL_PCD_Stop ,hpcd*HAL_PCD_IRQHandler ,hpcd*HAL_PCD_SOFCallbackc ,hpcd*#HAL_PCD_SetupStageCallback8 ,hpcd*HAL_PCD_ResetCallbackD ,hpcd* HAL_PCD_SuspendCallbacka ,hpcd*HAL_PCD_ResumeCallback ,hpcd* HAL_PCD_ConnectCallbacky ,hpcd*#HAL_PCD_DisconnectCallback3 ,hpcd*,epnum%HAL_PCD_DataOutStageCallback ,hpcd*,epnum$HAL_PCD_DataInStageCallback ,hpcd*,epnum)!HAL_PCD_ISOOUTIncompleteCallback> ,hpcd*,epnum( HAL_PCD_ISOINIncompleteCallback ,hpcd*HAL_PCD_DevConnectq ,hpcd*HAL_PCD_DevDisconnect+ ,hpcd*,addressHAL_PCD_SetAddressh ,hpcd*,ep_addr ,ep_mpsM,ep_typeHAL_PCD_EP_Open ,hpcd*,ep_addr HAL_PCD_EP_Closet ,hpcd*,ep_addr ,pBuf< , lenHAL_PCD_EP_Receive ,hpcd*,ep_addr ,pBuf< , lenHAL_PCD_EP_Transmit ,hpcd*,ep_addr HAL_PCD_EP_GetRxCountm ,hpcd*,ep_addr HAL_PCD_EP_SetStall8 ,hpcd*,ep_addr HAL_PCD_EP_ClrStallC ,hpcd*,ep_addr HAL_PCD_EP_Flushh ,hpcd*%HAL_PCD_ActivateRemoteWakeup< ,hpcd*'HAL_PCD_DeActivateRemoteWakeup ,hpcd*HAL_PCD_GetState=PUSB_WAKEUP_EXTI_LINEmPPCD_EP0MPS_64PPCD_EP0MPS_32PPCD_EP0MPS_16PPCD_EP0MPS_08P PCD_ENDP0,P PCD_ENDP1+P PCD_ENDP2*P PCD_ENDP3)P PCD_ENDP4(P PCD_ENDP5'P PCD_ENDP6&P PCD_ENDP7%P PCD_SNG_BUF[P PCD_DBL_BUFqPUSB_CNTRX_NBLK_MSKPUSB_CNTRX_BLSIZEPPCD_SET_ENDPOINTPPCD_GET_ENDPOINTPUSB_EP0StartXferPPCD_SET_EPTYPEWPPCD_GET_EPTYPEcPPCD_FreeUserBufferPPCD_SET_EP_TX_STATUS?PPCD_SET_EP_RX_STATUSAPPCD_SET_EP_TXRX_STATUSPPCD_GET_EP_TX_STATUSKPPCD_GET_EP_RX_STATUSMPPCD_SET_EP_TX_VALIDPPCD_SET_EP_RX_VALID#PPCD_GET_EP_TX_STALL_STATUS`#PPCD_GET_EP_RX_STALL_STATUSbPPCD_SET_EP_KINDPPCD_CLEAR_EP_KINDPPCD_SET_OUT_STATUSPPCD_CLEAR_OUT_STATUSlPPCD_SET_EP_DBUFPPCD_CLEAR_EP_DBUFPPCD_CLEAR_RX_EP_CTRPPCD_CLEAR_TX_EP_CTRP PCD_RX_DTOGHP PCD_TX_DTOGFPPCD_CLEAR_RX_DTOGvPPCD_CLEAR_TX_DTOGtPPCD_SET_EP_ADDRESS,PPCD_GET_EP_ADDRESS8PPCD_EP_TX_CNTPPCD_EP_RX_CNTPPCD_SET_EP_TX_ADDRESSPPCD_SET_EP_RX_ADDRESSPPCD_GET_EP_TX_ADDRESS'PPCD_GET_EP_RX_ADDRESS)PPCD_CALC_BLK32PPCD_CALC_BLK2PPCD_SET_EP_CNT_RX_REG PPCD_SET_EP_RX_DBUF0_CNTPPCD_SET_EP_TX_CNTDPPCD_SET_EP_RX_CNTFPPCD_GET_EP_TX_CNTPPPCD_GET_EP_RX_CNTRPPCD_SET_EP_DBUF0_ADDRaPPCD_SET_EP_DBUF1_ADDR`PPCD_SET_EP_DBUF_ADDRPPCD_GET_EP_DBUF0_ADDRmPPCD_GET_EP_DBUF1_ADDRlPPCD_SET_EP_DBUF0_CNTPPCD_SET_EP_DBUF1_CNTPPCD_SET_EP_DBUF_CNTPPCD_GET_EP_DBUF0_CNTPPCD_GET_EP_DBUF1_CNTPSTM32F1xx_HAL_HCD_HPSTM32F1xx_HAL_MMC_HHAL_MMC_STATE_RESETHAL_MMC_STATE_READYHAL_MMC_STATE_TIMEOUT\HAL_MMC_STATE_BUSYF"HAL_MMC_STATE_PROGRAMMING8 HAL_MMC_STATE_RECEIVINGHAL_MMC_STATE_TRANSFERHAL_MMC_STATE_ERRORHAL_MMC_StateTypeDef!HAL_MMC_CardStateTypeDef5PHAL_MMC_CARD_READYI$PHAL_MMC_CARD_IDENTIFICATIONPHAL_MMC_CARD_STANDBYPHAL_MMC_CARD_TRANSFERSPHAL_MMC_CARD_SENDINGPHAL_MMC_CARD_RECEIVING!PHAL_MMC_CARD_PROGRAMMINGo"PHAL_MMC_CARD_DISCONNECTED=PHAL_MMC_CARD_ERROR4PMMC_InitTypeDef,P MMC_TypeDef8 Q "φ CardTypeF "φClassr "φ RelCardAdd "φ BlockNbrU "φ BlockSize "φ LogBlockNbr- "φ LogBlockSize HAL_MMC_CardInfoTypeDef8 Q "؆ Instance "؆Init ""؆Lock "؆ pTxBuffPtrR "؆ TxXferSizeY "؆ pRxBuffPtrT "؆ RxXferSize[ "؆Contextv ""؆StateI "؆ ErrorCode "؆hdmarx "؆hdmatx "؆MmcCard <"؆CSDK <"؆CIDUMMC_HandleTypeDef8 Q " CSDStruct "SysSpecVersion " Reserved1 "TAAC> "NSAC2 "MaxBusClkFrec[ "CardComdClassesm " RdBlockLen "PartBlockReadG "WrBlockMisalignY "RdBlockMisalignl "DSRImpl " Reserved2 " DeviceSizeY "MaxRdCurrentVDDMinz "MaxRdCurrentVDDMaxx "MaxWrCurrentVDDMing "MaxWrCurrentVDDMaxe "DeviceSizeMul, " EraseGrSize " EraseGrMult "WrProtectGrSizeC "WrProtectGrEnable " ManDeflECC " WrSpeedFact "MaxWrBlockLenL "WriteBlockPaPartial " Reserved3 "ContentProtectAppli "FileFormatGroupK " CopyFlag: "PermWrProtect "TempWrProtect " FileFormatb "ECC "CSD_CRC@ " Reserved4HAL_MMC_CardCSDTypeDef`8 Q "ManufacturerID! " OEM_AppliID " ProdName1W " ProdName2] "ProdRev "ProdSNn " Reserved14 " ManufactDate "CID_CRC " Reserved23HAL_MMC_CardCIDTypeDefjPMMC_BLOCKSIZEPHAL_MMC_ERROR_NONE#PHAL_MMC_ERROR_CMD_CRC_FAIL$PHAL_MMC_ERROR_DATA_CRC_FAILp&PHAL_MMC_ERROR_CMD_RSP_TIMEOUT#PHAL_MMC_ERROR_DATA_TIMEOUT"PHAL_MMC_ERROR_TX_UNDERRUN!PHAL_MMC_ERROR_RX_OVERRUN&PHAL_MMC_ERROR_ADDR_MISALIGNED$PHAL_MMC_ERROR_BLOCK_LEN_ERRK$PHAL_MMC_ERROR_ERASE_SEQ_ERR<&PHAL_MMC_ERROR_BAD_ERASE_PARAM+P#HAL_MMC_ERROR_WRITE_PROT_VIOLATION)P!HAL_MMC_ERROR_LOCK_UNLOCK_FAILED%PHAL_MMC_ERROR_COM_CRC_FAILED "PHAL_MMC_ERROR_ILLEGAL_CMD&PHAL_MMC_ERROR_CARD_ECC_FAILEDPHAL_MMC_ERROR_CC_ERR|*P"HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR[+P#HAL_MMC_ERROR_STREAM_READ_UNDERRUN+P#HAL_MMC_ERROR_STREAM_WRITE_OVERRUN(P HAL_MMC_ERROR_CID_CSD_OVERWRITE$PHAL_MMC_ERROR_WP_ERASE_SKIP0(P HAL_MMC_ERROR_CARD_ECC_DISABLEDY"PHAL_MMC_ERROR_ERASE_RESET"PHAL_MMC_ERROR_AKE_SEQ_ERR(P HAL_MMC_ERROR_INVALID_VOLTRANGE(P HAL_MMC_ERROR_ADDR_OUT_OF_RANGE-P%HAL_MMC_ERROR_REQUEST_NOT_APPLICABLEPHAL_MMC_ERROR_PARAM*P"HAL_MMC_ERROR_UNSUPPORTED_FEATURE\PHAL_MMC_ERROR_BUSY PHAL_MMC_ERROR_DMA~PHAL_MMC_ERROR_TIMEOUT!PMMC_CONTEXT_NONE&PMMC_CONTEXT_READ_SINGLE_BLOCK(P MMC_CONTEXT_READ_MULTIPLE_BLOCK'PMMC_CONTEXT_WRITE_SINGLE_BLOCKY)P!MMC_CONTEXT_WRITE_MULTIPLE_BLOCKPMMC_CONTEXT_ITRPMMC_CONTEXT_DMAPMMC_HIGH_VOLTAGE_RANGEPMMC_DUAL_VOLTAGE_RANGE PeMMC_HIGH_VOLTAGE_RANGE PeMMC_DUAL_VOLTAGE_RANGE"PMMC_INVALID_VOLTAGE_RANGEPMMC_LOW_CAPACITY_CARDMPMMC_HIGH_CAPACITY_CARD%P__HAL_MMC_RESET_HANDLE_STATEP__HAL_MMC_ENABLEP__HAL_MMC_DISABLEP__HAL_MMC_DMA_ENABLEP__HAL_MMC_DMA_DISABLENP__HAL_MMC_ENABLE_ITP__HAL_MMC_DISABLE_ITP__HAL_MMC_GET_FLAG P__HAL_MMC_CLEAR_FLAGP__HAL_MMC_GET_ITP__HAL_MMC_CLEAR_IT ,hmmc$ HAL_MMC_Init ,hmmc$HAL_MMC_InitCardJ ,hmmc$HAL_MMC_DeInit ,hmmc$HAL_MMC_MspInit ,hmmc$HAL_MMC_MspDeInit ,hmmc$,pData,  BlockAdd, NumberOfBlocksG, TimeoutHAL_MMC_ReadBlocksz ,hmmc$,pData,  BlockAdd, NumberOfBlocksG, TimeoutHAL_MMC_WriteBlocks ,hmmc$, BlockStartAdd,  BlockEndAddHAL_MMC_Erasen ,hmmc$,pData,  BlockAdd, NumberOfBlocksGHAL_MMC_ReadBlocks_ITx ,hmmc$,pData,  BlockAdd, NumberOfBlocksGHAL_MMC_WriteBlocks_IT ,hmmc$,pData,  BlockAdd, NumberOfBlocksGHAL_MMC_ReadBlocks_DMAA ,hmmc$,pData,  BlockAdd, NumberOfBlocksG HAL_MMC_WriteBlocks_DMA ,hmmc$HAL_MMC_IRQHandler ,hmmc$HAL_MMC_TxCpltCallback ,hmmc$HAL_MMC_RxCpltCallback ,hmmc$HAL_MMC_ErrorCallback7 ,hmmc$HAL_MMC_AbortCallbackI ,hmmc$,  WideMode'HAL_MMC_ConfigWideBusOperation ,hmmc$HAL_MMC_GetCardState ,hmmc$ ,pCIDHAL_MMC_GetCardCID ,hmmc$ ,pCSDHAL_MMC_GetCardCSD ,hmmc$, pCardInfoIHAL_MMC_GetCardInfo, ,hmmc$HAL_MMC_GetState7 ,hmmc$HAL_MMC_GetError. ,hmmc$HAL_MMC_Abortf ,hmmc$HAL_MMC_Abort_ITdPUSE_FULL_ASSERTP assert_paramHAL_TICK_FREQ_10HZHAL_TICK_FREQ_100HZYHAL_TICK_FREQ_1KHZpHAL_TICK_FREQ_DEFAULTHAL_TickFreqTypeDef  uwTickPrio" uwTickFreq!P__HAL_DBGMCU_FREEZE_TIM2\#P__HAL_DBGMCU_UNFREEZE_TIM2!P__HAL_DBGMCU_FREEZE_TIM3[#P__HAL_DBGMCU_UNFREEZE_TIM3!P__HAL_DBGMCU_FREEZE_TIM4Z#P__HAL_DBGMCU_UNFREEZE_TIM4!P__HAL_DBGMCU_FREEZE_TIM5Y#P__HAL_DBGMCU_UNFREEZE_TIM5!P__HAL_DBGMCU_FREEZE_TIM6X#P__HAL_DBGMCU_UNFREEZE_TIM6!P__HAL_DBGMCU_FREEZE_TIM7W#P__HAL_DBGMCU_UNFREEZE_TIM7!P__HAL_DBGMCU_FREEZE_WWDG?#P__HAL_DBGMCU_UNFREEZE_WWDG!P__HAL_DBGMCU_FREEZE_IWDGM#P__HAL_DBGMCU_UNFREEZE_IWDG)P!__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT+P#__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUTL)P!__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT+P#__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUTK!P__HAL_DBGMCU_FREEZE_CAN1u#P__HAL_DBGMCU_UNFREEZE_CAN1!P__HAL_DBGMCU_FREEZE_TIM1]#P__HAL_DBGMCU_UNFREEZE_TIM1!P__HAL_DBGMCU_FREEZE_TIM8V#P__HAL_DBGMCU_UNFREEZE_TIM8P IS_TICKFREQa HAL_Init HAL_DeInitc HAL_MspInitHAL_MspDeInit-,  TickPriority HAL_InitTick} HAL_IncTick, Delay HAL_Delay HAL_GetTickHAL_GetTickPrioQ ,"Freq4HAL_SetTickFreqQHAL_GetTickFreq]HAL_SuspendTick)HAL_ResumeTickHAL_GetHalVersionw HAL_GetREVID HAL_GetDEVID HAL_GetUIDw0 HAL_GetUIDw1 HAL_GetUIDw2&HAL_DBGMCU_EnableDBGSleepMode'HAL_DBGMCU_DisableDBGSleepModeh%HAL_DBGMCU_EnableDBGStopMode,&HAL_DBGMCU_DisableDBGStopMode( HAL_DBGMCU_EnableDBGStandbyMode)!HAL_DBGMCU_DisableDBGStandbyModePSYSTEM_SUPPORT_OS' s32# s16! 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